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Latch preventing dual-node-flipping

A dual-node inversion and latch technology is applied in fields such as reliability improvement of field effect transistors, logic circuit coupling/interface using field effect transistors, and reliability improvement modification. Problems such as double-node flipping achieve low area overhead, improved ability to resist single event flipping, and high reliability

Active Publication Date: 2018-05-18
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present application solves the technical problem that the latch in the prior art cannot realize anti-double-node flipping in a small-area circuit structure by providing a latch that resists double-node flipping, so that the latch provided by the present application The device achieves the technical effects of improving the ability of digital integrated circuits to resist single event flipping under harsh conditions, resisting double-node flipping, high reliability, and low area overhead

Method used

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Embodiment 1

[0027] figure 1 It is a schematic structural diagram of a latch resistant to double-node flipping provided by an embodiment of the present application. Such as figure 1 shown, the latch consists of:

[0028] The latch has a storage node A, a storage node B, a storage node C, a storage node D, a storage node E, a storage node F, and a storage node G;

[0029] Specifically, a latch (Latch) is a memory unit circuit sensitive to a pulse level, and they can change states under the action of a specific input pulse level. Latch is to temporarily store the signal to maintain a certain level state. The main function of the latch is to cache, secondly to complete the asynchronous problem between the high-speed controller and the slow peripheral, then to solve the problem of the driver, and finally to solve the problem that an I / O port can output and input question. A latch is an input that uses level control data, and it includes a latch without enable control and a latch with enab...

Embodiment 2

[0038] In order to further explain the anti-double-node flipping latch provided in the present application, the embodiment of the present application describes the working principle of the anti-double-node flipping latch.

[0039] When the latch is in conduction mode, as Figure 4 As shown, the input data In are transmitted to storage node A, storage node C and storage node F through CMOS transmission gates TG1, TG2 and TG3 respectively, while storage node B, storage node D, storage node E and storage node G are connected with the input data In is logically the opposite. D is output to the output node Q through a clocked inverter, so the input In is logically the same as the output Q. In holdover mode, these redundant nodes have the ability to restore the correct logic. As a result, when the dual-node flip occurs, it can be restored to the normal logic level by the remaining storage nodes, which improves the ability of digital integrated circuits to resist single-event flipp...

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Abstract

The embodiment of the invention provides a latch preventing dual-node-flipping, and relates to the technical field of integrated circuits. The latch comprises a storage node A, a storage node B, a storage node C, a storage node D, a storage node E, a storage node F, and a storage node G; the latch further comprises a first cross-coupling structure; a second cross-coupling structure; a third cross-coupling structure; a fourth cross-coupling structure; a fifth cross-coupling structure; a sixth cross-coupling structure; a seventh cross-coupling structure; an eighth cross-coupling structure; and aninth cross-coupling structure. The technical problem that the latch in the prior art cannot prevent dual-node-flipping in a small-area circuit structure is solved, so that the latch provided by theinvention achieves the technical effects of improving the single event upset ability of digital integrated circuits, preventing dual-node-flipping preventing, and ensuring high reliability and low area overhead under severe conditions.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a double-node flip-resistant latch. Background technique [0002] A latch (Latch) is a memory cell circuit that is sensitive to pulse levels, and they can change states under the action of a specific input pulse level. Latch is to temporarily store the signal to maintain a certain level state. One of the functions of the latch is to solve the problem that an I / O port can both output and input. [0003] However, in the process of realizing the technical solution of the invention in the embodiment of the present application, the inventor of the present application found that the above-mentioned technology has at least the following technical problems: [0004] The latches in the prior art cannot realize anti-double-node flipping in a small-area circuit structure. Contents of the invention [0005] The embodiment of the present application solves the technical probl...

Claims

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Application Information

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IPC IPC(8): H03K19/003H03K19/0185
CPCH03K19/00315H03K19/018507
Inventor 刘梦新刘海南赵发展卜建辉罗家俊韩郑生
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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