Package structure and fabrication method thereof

Abstract

This disclosure provides a package structure and a fabrication method thereof. The package structure includes a conductive pattern layer having a bump region and a wiring region, the bump region comprising a plurality of conductive bumps and a first dielectric material surrounding the plurality of conductive bumps, the wiring region comprising a plurality of first conductive wires and a second dielectric material covering and surrounding the plurality of first conductive wires; a circuit device with a plurality of connecting terminals disposed on the bump region, each of the connecting terminals corresponding with one of the conductive bumps; an insulation sealant formed on the second dielectric material and around sidewalls of the circuit device; and a third dielectric material covering the circuit device and the wiring region.

Description

technical field [0001] The invention relates to a packaging structure suitable for large-area rectangular panel manufacturing and a manufacturing method thereof. Background technique [0002] The new generation of electronic products not only pursues thin, short and high density, but also tends to develop towards high power; therefore, the integrated circuit (Integrated Circuit, IC) technology and its back-end chip packaging technology are also developing to meet this new trend. Performance specifications for a generation of electronic products. [0003] The current packaging method with the wafer size as the base can be described with reference to FIG. Figure 1A As shown; then the semiconductor chip 13 or the pin 16 of the electronic component 15 faces down and is pasted on the wafer carrier plate 11 by virtue of the adhesive layer 18, and then the mold compound 12 is used to cover and package the semiconductor chip by molding technology 13 or electronic components 15 suc...

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Problems solved by technology

However, in order to achieve the above-mentioned requirements on the flatness of the upper surface 21, the wafer carrier plate 11 and the adhesive layer 18 must be relatively expensive, and the semiconductor wafer 13 and the electronic components 15 must be precisely and slowly Paste on the adhesive layer 18 in a manner; this is not conducive to the manufacture of a large-area rectangular panel (Panel) form, and will increase the manufacturing cost of the package component

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