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A multi-core cache wcet analysis method that supports instruction prefetching

A technology of instruction prefetching and analysis methods, applied in reliability/availability analysis, instrumentation, error detection/correction, etc., capable of solving complex tasks such as WCET estimation and conservatism

Inactive Publication Date: 2020-10-27
BEIJING INSTITUTE OF TECHNOLOGYGY
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The purpose of the present invention is to overcome the limitations of the existing multi-core shared cache WCET analysis technology that is too complex and the task WCET estimation is too conservative, and proposes a multi-core cache WCET analysis method that supports instruction prefetching

Method used

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  • A multi-core cache wcet analysis method that supports instruction prefetching
  • A multi-core cache wcet analysis method that supports instruction prefetching
  • A multi-core cache wcet analysis method that supports instruction prefetching

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Embodiment 1

[0101] This embodiment describes in detail the execution process of the present invention when it is implemented in the case of instruction prefetching.

[0102] figure 1 It is a flow chart of the WCET analysis method of the present invention, and each block in the figure represents an operation step of the present invention. figure 2 It is a flow chart of the basic block analysis in the present invention, and the L1 cache state analysis and the L2 cache state analysis of the basic block in the task are all adopted figure 2 in the steps. image 3 (a-c) describe part of the source code of a program, and its corresponding CFG and assembly code obtained through reverse analysis. image 3 A node in (b) represents the number of the basic block, for example, B0 means that the number of the basic block is 0. for image 3 (c) The PISA assembly code based on the Simplescalar simulator in the basic block, the number at the top of each line is the instruction number (1-10), and the...

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Abstract

The invention relates to a multi-core cache WCET analysis method supporting instruction prefetching, and belongs to the technical field of embedded real-time system application. Accordingly, on the basis of the shared-cache-based multi-core cache structure, for the WCET analysis problem in instruction prefetching, and by expanding instruction prefetching semantics, cache is instructed to access classification in advance, and then the influence of instruction prefetching on the private L1 instruction cache state and the shared L2 instruction cache state is analyzed. Therefore, the accuracy of application program WCET analysis is improved. The method can be widely applied to schedulable analysis of tasks in a real-time system, and then an accurate and compact WCET assessment value is obtained.

Description

technical field [0001] The invention relates to a task worst case execution time (Worst Case Execution Time, WCET) analysis method, in particular to a multi-core cache WCET analysis method supporting instruction prefetching, belonging to the field of embedded real-time system applications. Background technique [0002] With the rapid development of semiconductor technology, multi-core processors have been widely used in embedded real-time control systems such as drones, high-speed rail, automobiles, and factory automation. Different from traditional general-purpose computer systems, in such embedded real-time systems, the task execution has strict time constraints, and all tasks in the system must be completed before the specified deadline, otherwise serious or even catastrophic consequences may occur. Therefore, when designing such a real-time system, it is necessary to know the WCET estimation of the task in the system in advance, and the process of obtaining the worst-cas...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/00G06F11/34
CPCG06F11/008G06F11/3409G06F11/3452G06F2201/885
Inventor 付引霞甘志华张铭泉安立奎古志民
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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