Via circuit of switching power domain parallel interface to normally open power domain parallel interface

Abstract

The invention discloses a via circuit of a switching power domain parallel interface to a normally open power domain parallel interface. The via circuit comprises a control signal detection circuit and an interface control circuit. A control signal detection module is connected with the switching power domain parallel interface through data, an address bus, control signals, transmission response signals, and handshaking signals. The control signal detection circuit detects reading-writing control signals, and latches effective data and addresses. In the interface control circuit, a response signal is set, and the response signal is sent to the control signal detection module when data transmission is completed, and the interface control circuit controls the handshaking signals of the signal detection module. Through the interface control circuit and the control signal detection circuit, the number of control signals of a normally open voltage domain interface circuit is reduced, the number of level shifters inserted between two power domains is reduced, and area is saved. Also, in the period of data transmission, data transmission is realized through the handshaking signals, a system bus is not occupied, and performance of the system is improved.

Description

technical field [0001] The invention relates to a switching circuit, in particular to a circuit for realizing interface communication between different power domains. Background technique [0002] In the low-power design, the SOC modules are divided into multiple voltage domains, and the driving capabilities of different voltage domains will be different, resulting in the limitation of the operating frequency in different voltage domains, and in different voltage domains. Each digital module needs to frequently interact with data. One way to achieve this is to increase the data writing completion flag, and the processor CPU can judge whether the writing is successful by querying the flag, and requires each write to the module After that, the flag must be queried. [0003] The defect of above-mentioned realization mode is: the one, when transmitting data, system bus is in busy state, can not carry out other operation again, has reduced the performance of system; For the lev...

AI Technical Summary

Problems solved by technology

[0003] The defect of above-mentioned implementation mode is: the one, when transmitting data, system bus is in busy state, can not carry out other operation again, has reduced the performance of system; For the levelshifter) the number of circuits is large, which increases the area cost

Images