Decoupled processor instruction window and operand buffer

Abstract

A processor core in an instruction block-based microarchitecture is configured so that an instruction window and operand buffers are decoupled for independent operation in which instructions in the block are not tied to resources such as control bits and operands that are maintained in the operand buffers. Instead, pointers are established among instructions in the block and the resources so thatcontrol state can be established for a refreshed instruction block (i.e., an instruction block that is reused without re-fetching it from an instruction cache) by following the pointers. Such decoupling of the instruction window from the operand space can provide greater processor efficiency, particularly in multiple core arrays where refreshing is utilized (for example when executing program codethat uses tight loops), because the operands and control bits are pre-validated.

Description

Background technique [0001] Designers of instruction set architectures (ISAs) and processors make tradeoffs between power consumption and performance. For example, if the designer selects an ISA with instructions that deliver higher performance, the processor's power consumption may also be higher. Alternatively, performance may be lower if the designer chooses an ISA with instructions that consume less power. Power consumption may be related to the amount of a processor's hardware resources, such as an arithmetic logic unit (ALU), cache lines, or registers, used by an instruction during execution. Using a large number of such hardware resources can deliver higher performance at the expense of higher power consumption. Alternatively, using fewer such hardware resources can result in lower power consumption at the expense of lower performance. A compiler can be used to compile high-level code into instructions compatible with the ISA and processor architecture. Contents of...

AI Technical Summary

Problems solved by technology

For example, if the designer selects an ISA with instructions that deliver higher performance, the processor may also consum

Images