Data prefetching system and method applied to SOC architecture

Abstract

The invention provides a data prefetching system applied to an SOC architecture and a memory access method. The system comprises a CPU, an AHB bus, a quick access engine and a memory, wherein the CPUis connected with the AHB bus and used for sending an address fetching instruction to the AHB bus; the quick access engine is used for receiving the address fetching instruction of the CPU from the AHB bus and judging whether the address fetching instruction has corresponding prefetching operation in the quick access engine; if yes, a response is directly made; and otherwise, the memory is accessed according to the address fetching instruction, an address fetching value corresponding to the address fetching instruction is saved into the quick access engine, a response is made to the CPU, and meanwhile adjacent address values of the address fetching value are fetched and saved into a cache of the quick access engine. Compared with the prior art, the quick access engine is added between theCPU and the memory, address prefetching judgment and operation are performed before the CPU sends the address fetching instruction to the memory, and when the address fetching instruction of the CPU really arrives, the effect of direct responding without waiting can be achieved.

Description

technical field [0001] The invention relates to the field of SOC architecture, in particular to a data prefetching system and a prefetching method for the SOC architecture. Background technique [0002] A SOC (system on chip) generally includes at least a central processing unit (CPU) and a storage device (memory) for storing programs, and in addition, some peripheral devices may be added in order to realize specific or general functions. [0003] However, the interface specification of the currently used CPU complies with AMBA-related protocols, that is, it needs to interact with other peripherals through the AMBA bus, so all peripherals are connected to the AMBA bus. Among them, AMBA bus includes AHB, ASB and APB bus. The more commonly used buses are AHB and APB. Generally, peripherals that require high-speed access are all AHB interfaces. Peripherals that do not require high access rates are generally connected to the APB bus, and ASB is rarely used. [0004] Please als...

AI Technical Summary

Problems solved by technology

[0006] Since the operating frequency of the CPU is often higher than the frequency of the memory, the CPU has to wait for several clock cycles to obtain a response from the memory every time the CPU issues an instruction to operate on the memory, which greatly reduces the operating efficiency of the CPU.

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