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Memory management method and memory management apparatus related to quick access memory in image processing system

A technology of memory management and memory, which is applied in the direction of image memory management, data processing input/output process, electrical digital data processing, etc., and can solve the problem of low frequency of cache columns being used, underutilization of hardware resources, and utilization of uneven rate

Inactive Publication Date: 2018-03-13
MEDIATEK INC
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Problems solved by technology

[0007] However, by Figure 1(A) ~ Figure 1(D) It can also be seen that in the case of compressing image blocks, the cache lines closer to the arrow 110 in the storage area 100 will be used more frequently, while the cache lines farther away from the arrow 110 will be used. The frequency is obviously lower
This uneven utilization indicates that some hardware resources are not fully utilized

Method used

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  • Memory management method and memory management apparatus related to quick access memory in image processing system
  • Memory management method and memory management apparatus related to quick access memory in image processing system
  • Memory management method and memory management apparatus related to quick access memory in image processing system

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Embodiment Construction

[0032] A specific embodiment according to the present invention is a memory management method applied to a cache memory including multiple storage areas. The flowchart of the memory management method is shown in figure 2 . image 3 An example of a cache memory internal configuration that may be used to implement the memory management method 200 is presented. Cache memory 300 includes sixty-four cache ranks. It is assumed that the compressed data volume of each image block occupies at most the storage space of eight cache rows. The cache memory 300 can be planned to include eight storage areas, and each storage area includes eight cache rows. In this embodiment, the eight storage areas are numbered as storage area #0˜storage area #7. Taking the original picture containing forty-eight image blocks shown in FIG. 4(A) as an example, each storage area in the cache memory 300 can be designed to correspond to six (=48 / 8 ) different image blocks. In practice, the corresponding ...

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Abstract

The invention provides a memory management method related to a quick access memory in an image processing system. The method is applied to the quick access memory comprising multiple storage regions.Each storage region comprises multiple quick access columns and corresponds to multiple image blocks in an original image. In response to a request of storing compressed data of an image block in thequick access memory, a storage region corresponding to the image block is selected as a target storage region. Then, a target quick access column use sequence suitable for the image block is determined. Further, the image block claims the compressed data to be stored in the target storage region, so that the compressed data of the image block conforms to the target quick access column use sequenceafter being stored in the target storage region.

Description

technical field [0001] The present invention is related to memory, and in particular to the management technology of cache for storing image data. Background technique [0002] In electronic systems, cache memory is used to temporarily store a small amount of data that has just been used or will be used by the processor in the near future. Compared with the main memory with larger capacity, the cache memory can access data faster, but the hardware price is higher. Generally speaking, the main memory is realized by dynamic random access memory (DRAM), and the cache memory is realized by static random access memory (SRAM). When a specific piece of data is needed, the processor will first look for it in the cache memory, and if the piece of data cannot be found, it will turn to the main memory for looking for it. When the target data is successfully found in the cache memory, it is called a cache hit, and if it fails, it is called a cache miss. [0003] A cache memory includ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06G06T1/60
CPCG06F3/061G06F3/0638G06F3/0671G06T1/60
Inventor 林和源
Owner MEDIATEK INC
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