Memory access system and method

Abstract

A memory access system and method, the system comprising: a memory (21), a controller (23) and a redundancy elimination unit (22); the memory is a multi-way group memory (21); the redundancy elimination Unit (22) records M record items, and each record item is used to preserve the label of the stored data block in each storage group; the controller (23) determines the read data block and the read data block the target storage group, sending a query message to the redundancy elimination unit (22), the query message carrying the group identifier of the target storage group of the read data block and the label of the read data block; the redundancy elimination The unit (22) determines the record item corresponding to the group identifier of the target storage group according to the group identifier of the target storage group of the read data block, and associates the label of the read data block with the target storage group of the read data block The tags of the stored data blocks in the corresponding record items are matched, and if the matching fails, a query response message of read data miss is sent to the controller (23).

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a memory access system and method. Background technique [0002] On-chip high-speed cache (Cache) is an essential component in various types of processors such as single-core processors, multi-core processors, and many-core processors. The current cache structure generally adopts a way-set associative structure. However, when accessing a cache whose way groups are connected, it is necessary to enable all the cache ways (N ways) in the cache, and set the flag bit (Tag) fetched from the memory access address to all cache lines corresponding to the memory access address. The flag bits are compared in parallel, and the comparison result is obtained whether it is the same as one of the flag bits in the cache line. Each parallel comparison is at most the same as one of the flags in the cache line, and at this time it is called a cache hit (Cache Hit), that is, even in the case of a hit...

AI Technical Summary

Problems solved by technology

[0003] In multi-core processors, such as SMT processors, when multiple hardware threads share the cache, the probability that the cache blocks in the same cache line belong to the same thread is reduced, that is, after a cache block has been occupied by a thread, if When another thread also needs to access this cache block, all storage paths need to be enabled. After N times of tag comparison, it can be determined that the access is missing, and then the data in the cache block is replaced, and the data that needs to be accessed is retrieved from the memory. Therefore, the ratio of cache blocks occupied by different threads is increased, which makes the problem of cache redundant access more serious.

Images