MOS power device and manufacturing method thereof

Abstract

The present invention discloses a MOS (Metal Oxide Semiconductor) power device and a manufacturing method thereof. The method comprises the steps that: generating a first insulation dielectric layer,a first semiconductor layer, a second insulation dielectric layer and a second semiconductor layer in order above the substrate, and forming a first multi-layer structure; performing etching on the first multi-layer structure until a partial region of the first insulation dielectric layer is exposed, and forming a second multi-layer structure; injecting impurities in the substrate to form a well region and source region in the substrate, and obtaining a third multi-layer structure; depositing a third insulation dielectric layer above the third multi-layer structure, and forming a fourth multi-layer structure; performing etching of the fourth multi-layer structure through a self-aligned mode, forming a connection hole, and forming a fifth multi-layer structure; and depositing a metal layerabove the fifth multi-layer structure, and forming an emission electrode. Therefore, migration is avoided, and consistency and stability of performance parameters of an MOS power device can be ensured.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a MOS type power device and a manufacturing method thereof. Background technique [0002] MOS specifically refers to a metal oxide semiconductor structure. Any device with a MOS structure is called a MOS power device. Existing MOS power devices such as IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor), MOSFET (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor), MOS capacitor, etc., adopt voltage control mode , has the advantages of fast switching speed and simple control circuit, and is widely used in modern power electronic systems. [0003] figure 1 It is a structural schematic diagram of an existing MOS type power device. Such as figure 1 As shown, the existing MOS power device includes a silicon substrate 101 , an insulating medium 102 , a gate 103 , a well region 104 , a source region 105 , an insu...

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Problems solved by technology

[0014] This kind of offset may cause two problems: 1. Devices manufactured in different periods have different offset directions and distances, resulting in inconsistent device structures and unstable performance parameters; 2. In order to ensure that the gate and emitter The safety isolation between them needs to consider the maximum offset. In this way, the distance between the connection hole and the gate must be large in the design

Therefore, the size of the entire MOS type power device is larger and the manufacturing cost is higher

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