CPLD-based clock counting method and device, and medium

Abstract

The invention discloses a CPLD-based clock counting method and device, and a medium. The method comprises the following steps: acquiring an event duration of a CPLD, and setting layers representing counting cycles according to the event duration, wherein the layers at least comprise two layers, the lowest layer represents a system cycle, durations of the counting cycles are positively related to layer levels, and the counting cycle represented by a higher layer is an integer multiple of the counting cycle represented by a lower layer; starting counting by using the counting cycle represented by the lowest of the layers as a current cycle, and using a target counting cycle represented by a next layer as the current cycle to continue the counting when a counting duration reaches the target counting cycle, until the current cycle is identical to the counting cycle represented by the highest of the layers; and continuing the counting according to the current cycle to reach the event duration. Therefore, the method provided by the invention has the beneficial effect that the overall work efficiency of the CPLD during clock counting is relatively improved. Moreover, the invention furtherprovides the CPLD-based clock counting device, and the medium, which achieve the above beneficial effect.

Description

technical field [0001] The present invention relates to the field of CPLD, in particular to a clock counting method, device and medium based on CPLD. Background technique [0002] The clock is a very important part of the logic system. All sequential logic modules require the clock as a synchronization signal for execution. [0003] In the huge logic system of CPLD, the user's time requirement for the clock often spans from the microsecond level to the second level, and there is a big difference in the consumption of CPLD logic resources with different durations. The clock counting scheme adopted by the current CPLD takes the system clock duration as the basic clock duration, and performs the clock counting operation in combination with the counter. For example, if the system clock is 50MHz, that is, the system period is 20ns. If a clock signal with a duration of 1us needs to be generated, the counter needs to count 50 times (1us / 20ns=50), and 50 needs a 6-bit binary number...

AI Technical Summary

Problems solved by technology

It can be seen that when the duration of the clock signal is longer, the more digits of the counter are required, and in the CPLD, the logic unit provides the counting digits used by the counter, but when the logic unit is used to provide the counting digits, the logic unit cannot Reuse for other logical operations

However, the number of logic units in the CPLD is relatively scarce, so when the above-mentioned clock counting scheme is adopted and the signal duration is long, the logic unit occupies a large amount, which relatively reduces the overall working efficiency of the CPLD.

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