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Shift register unit, driving method thereof, gate driving circuit and display device

A technology of shift register unit and gate, which is applied in the field of gate drive circuit, display device, and shift register unit, can solve the problems of unfavorable narrow frame design and the like

Active Publication Date: 2018-01-26
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, with the gradual improvement of the resolution of the display panel, the number of shift register units in the gate driving circuit is gradually increasing, which is not conducive to the design of narrow borders.

Method used

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  • Shift register unit, driving method thereof, gate driving circuit and display device
  • Shift register unit, driving method thereof, gate driving circuit and display device
  • Shift register unit, driving method thereof, gate driving circuit and display device

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0146] by image 3 The shift register unit shown is taken as an example, where CN=1, CNB=0, VGH=1, VGL=0, and the corresponding timing diagram is shown in FIG. 13 .

[0147] In the PI phase, IN=1, Reset=0, CK1=0, CK2=0, CK3=0, CK4=0.

[0148] IN=1, the first switch transistor T1 is turned on, the high potential signal of the first reference potential terminal CN is transmitted to the first node PUCN through the turned on first switch transistor T1, the potential of the first node PUCN is high potential, and the sixth The switching transistor T6 is turned on. Since VGH=1, the ninth switching transistor T9 1 and T9 2 is turned on, the potentials of the first control node PU1 and the second control node PU2 are high potential, and the eighth switching transistor T8 1 and T8 2 is turned on, the low potential signal of the third clock signal terminal CK3 passes through the turned-on eighth switch transistor T8 1 transmitted to the first output terminal OUT1, the potential of ...

example 2

[0161] by Figure 5 The shift register unit shown is taken as an example, where CN=1, CNB=0, VGH=1, VGL=0, and the corresponding timing diagram is shown in FIG. 13 .

[0162] In the PI phase, IN=1, Reset=0, CK1=0, CK2=0, CK3=0, CK4=0.

[0163] Tenth switching transistor T10 1 and T10 2 When it is off, the working states of the other switching transistors are the same as the P1 stage of the first example, and will not be repeated here.

[0164] In the P2 phase, IN=0, Reset=0, CK1=0, CK2=0, CK3=1, CK4=0.

[0165] Tenth switching transistor T10 1 and T10 2 When it is off, the working states of the other switching transistors are the same as the P2 stage of the first example, and will not be repeated here.

[0166] In the P3 phase, IN=0, Reset=0, CK1=0, CK2=0, CK3=0, CK4=1.

[0167] Tenth switching transistor T10 1 and T10 2 When it is off, the working states of the other switching transistors are the same as the P3 stage of the first example, and will not be repeated her...

example 3

[0176] Apply to the shift register unit Figure 11 gate drive circuit shown, and with Figure 5 Take the shift register unit shown as an example, and the corresponding timing is as follows Figure 14 shown.

[0177] In the PI phase, IN=1, Reset=0, CK1=0, CK2=0, CK3=0, CK4=0.

[0178] The working state is the same as that of the P1 stage of the second example, and will not be repeated here.

[0179] In the P2 phase, IN=0, Reset=0, CK1=0, CK2=0, CK3=1, CK4=0.

[0180] The working state is the same as that of the P2 stage of the second example, and will not be repeated here.

[0181] In the P3 phase, IN=0, Reset=0, CK1=0, CK2=0, CK3=0, CK4=1.

[0182] The working state is the same as that of the P3 stage of the second example, and will not be repeated here.

[0183] In the P4 stage, IN=0, Reset=1, CK1=1, CK2=0, CK3=0, CK4=0.

[0184] The working status is the same as that of the P5 stage of the second example, and will not be repeated here.

[0185]In the P5 stage, IN=0, ...

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Abstract

The invention discloses a shift register unit, a driving method thereof, a gate driving circuit and a display device. The shift register unit comprises a first input module, a second input module, a first node control module, a second node control module, a third node control module and N output modules, and is characterized in that the first input module, th second input module and the first nodecontrol module are used for performing control on a first node; the second node control module is used for performing control on a second node so as to facilitate the third node control module to perform control on a third node according to the second node and the first node, and the N output modules perform control on corresponding output terminals according to corresponding clock signal terminals under the control of the first node. The shift register unit controls the plurality of output terminals through the plurality of output modules, so that one shift register unit can be connected toa plurality of grid lines, and the number of the shift register unit can be reduced when the shift register unit is applied to a display panel, thereby being conducive to the narrow-frame design.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a shift register unit, a driving method thereof, a gate driving circuit and a display device. Background technique [0002] In a thin film transistor display, generally a gate driving circuit provides a gate driving signal to the gate of each thin film transistor (TFT, Thin Film Transistor) in the pixel area. The gate drive circuit can be formed on the array substrate of the liquid crystal display through an array process, that is, the gate driver on array (GOA) process of the array substrate. The beautiful design is symmetrical on both sides, and at the same time, it also saves the bonding (Bonding) area of ​​the gate integrated circuit (IC, Integrated Circuit) and the wiring space of the fan-out (Fan-out), so that the design of the narrow border can be realized; and , This integration process can also save the Bonding process in the direction of the gate scanning line, thereb...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/36G11C19/28
CPCG11C19/28G09G3/3677G09G2310/0286G09G2300/0426G09G2310/08
Inventor 付弋珊樊君张寒李付强
Owner BOE TECH GRP CO LTD
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