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Stream reference register with double vector and dual single vector operating modes

A technology of registers and data registers, applied in memory systems, instruments, machine execution devices, etc., can solve problems such as difficult address generation and access resources

Pending Publication Date: 2018-01-16
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Often the corresponding memory accesses are difficult to achieve with the available address generation and memory access resources

Method used

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  • Stream reference register with double vector and dual single vector operating modes
  • Stream reference register with double vector and dual single vector operating modes
  • Stream reference register with double vector and dual single vector operating modes

Examples

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Embodiment Construction

[0044] figure 1 A dual scalar / vector datapath processor in accordance with a preferred embodiment of the present invention is described. The processor 100 includes separate L1 instruction register (L1I) 121 and L1 data register (L1D) 123 . Processor 100 includes a combined level two instruction / data cache (L2) 130, which holds both instructions and data. figure 1 The connection (bus 142 ) between the L1 instruction register 121 and the L2 combined instruction / data register 130 is illustrated. figure 1 The connection between the L1 data cache 123 and the L2 combined instruction / data cache 130 (bus 145) is illustrated. In a preferred embodiment of the processor 100 , the L2 combined I / D cache 130 stores both instructions to back up the L1 Irreg 121 and stores data to back up the L1 data cache 123 . In a preferred embodiment, the two-level combined instruction / data cache 130 is further implemented with known but figure 1 connection to higher-level cache and / or main memory in ...

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Abstract

The streaming engine (3100) fetches a fixed read-only data stream and packs the stream header data into two headend registers (3118 / 3119). The instruction decoder (113) decodes the instruction operandfield (1305) to control the data supply to the functional units (3230, 3240). The sub-decoder (3211) supplies the data from the general register file (231) to the functional unit (3230). The read-only operation sub-decoder (3215) supplies data from the first head-end register (3118). Read / advance operand sub-decoder (3216) supplies data and advances streams. The corresponding read only operandsub-decoder (3217) and read / early operand sub-decoder (3218) operate similarly using the second head register (3119). The read-only operand sub-decoder (3213) supplies double-width data from the twohead-end registers (3118, 3119) to the function unit (3230) and the pairing function unit (3240). The read / advance operand sub-decoder (3214) supplies double-width data and advances the stream.

Description

[0001] related application [0002] This patent application is an improvement over U.S. Patent Application Serial No. 14 / 331,986, filed July 15, 2014, and entitled "HIGHLYINTEGRATED SCALABLE, FLEXIBLE DSP MEGAMODULE ARCHITECTURE," which claims the serial number filed on July 15, 2013 Priority to US Provisional Patent Application 61 / 846,148. technical field [0003] The technical field of the invention is digital data processing, and more specifically the control of streaming engines for operand extraction. Background technique [0004] Modern digital signal processors (DSPs) face multiple challenges. Increasing workloads require increased bandwidth. Systems-on-a-chip (SOCs) continue to grow in size and complexity. Certain types of algorithms are severely affected by memory system latency. As transistors get smaller, memory and registers become less reliable. As the software stack becomes larger, the number of possible interactions and errors becomes larger. [0005] Fo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G06F9/32G06F9/38G06F12/0811G06F12/0815G06F12/0875
CPCG06F9/30036G06F9/30047G06F9/345G06F9/3824G06F9/383G06F9/30065G06F9/30149G06F9/3016G06F12/0875G06F2212/452
Inventor J·茨维西亚克
Owner TEXAS INSTR INC
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