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Postprocessing decoding method of LDPC codes based on CRC check codes

A technology of LDPC code and check code, which is applied in the field of post-processing and decoding of LDPC code based on CRC code, can solve the problems of lower bit error rate, unsatisfactory error floor and lower error floor, etc., and achieve the goal of improving reliability Effect

Active Publication Date: 2017-12-29
GUILIN UNIV OF ELECTRONIC TECH
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Problems solved by technology

E. Likhobabin et al. proposed the method of variable node deletion, which directly deletes the variable nodes whose symbols have changed in the two iterations before and after, so as to reduce the error floor. The error floor under the signal-to-noise ratio is still not ideal, and the bit error rate needs to be further reduced

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  • Postprocessing decoding method of LDPC codes based on CRC check codes
  • Postprocessing decoding method of LDPC codes based on CRC check codes
  • Postprocessing decoding method of LDPC codes based on CRC check codes

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Embodiment

[0031] refer to figure 1 , a kind of LDPC code post-processing decoding method based on CRC check code, comprises the steps:

[0032] 1) Execute the LBP decoding method;

[0033] 2) CRC check: at the end of the step 1) LBP decoding method, the CRC check is performed on the decoding judgment result, and the CRC check judgment is executed. If the check is successful, the decoding is judged to be successful and the decoding is stopped, otherwise, the next step is performed. step;

[0034] 3) LLR value sorting: arrange the posterior LLR values ​​of the variable nodes in the error frame in ascending order to obtain an ordered node sequence;

[0035] 4) Selection of target nodes: select the first several target nodes from the sorted node sequence to form a BN set;

[0036]5) Node flipping: turn over the initial LLR values ​​of the information nodes in the BN set in turn;

[0037] 6) CRC check again: In the post-processing stage, perform CRC check on the decoding judgment result ...

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Abstract

The present invention discloses a postprocessing decoding method of LDPC (Low Density Parity-Check) codes based on CRC (Cyclic Redundancy Check) check codes. The method comprises the following steps: 1) executing a LBP (Layered Belief-Propagation) decoding method; 2) performing CRC verification; 3) performing LLR (Log-Likelihood Ratio) value sorting; 4) selecting target node; 5) performing node overturning; and 6) performing CRC verification again: a decoding decision result is subjected to CRC verification again at a postprocessing phase, if the verification is successful, the decoding is successful and is finished, or else, the process jumps to the step 5) to go on overturning. The method provided by the invention can perform overturning of error bits in order at the subsequent processing phase of error frames to damage a potential trapping set and improve the error floor while ensuring low decoding complexity.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a CRC (Cyclic Redundancy Check, CRC for short) code-based LDPC (Low Density Parity-Check, LDPC for short) code post-processing decoding method. Background technique [0002] LDPC code is a linear block code first proposed by Dr. Gallager in 1962. Because of its excellent characteristics of being close to the Shannon limit and low decoding complexity, it is widely used in DVB-S2, WiMax and deep space communication, etc. In the communication standard, however, the error floor caused by the trap set makes the LDPC code unable to obtain a very low bit error rate in the high signal-to-noise ratio area, which seriously restricts the application of the LDPC code in data storage and optical communication systems that require high reliability data transmission. Applications. In response to this problem, domestic and foreign researchers began to try to use different methods to redu...

Claims

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Application Information

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IPC IPC(8): H03M13/11H03M13/09
CPCH03M13/09H03M13/1125
Inventor 陈紫强王广耀黄志成周秉毅刘庆华谢跃雷欧阳缮蒋俊正晋良念
Owner GUILIN UNIV OF ELECTRONIC TECH
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