Method and system for recovering low-speed data through high-speed serdes interface

Abstract

The invention discloses a method and system for recovering low-speed data through a high-speed SerDes interface, and relates to the technical field of communications. The method comprises the following steps that input low-speed data is converted into sampling parallel data through the high-speed SerDes interface, wherein the bit width of the sampling parallel data is an integral multiple of the sampling rate m; the sampling parallel data is extracted in a batched mode to serve as target data, the data bit number of the target data of each batch is the same as the bit width of the sampling parallel data, and after 1 bit displacement is conducted on the target data, the displaced target data is subjected to pairwise xor to obtain the jump edge position of the sampling parallel data; the sampling point position of the sampling parallel data is determined according to the jump edge position, the data corresponding to the sampling point position is effective data of the low-speed data, and the effective data is extracted from the sampling point position of the sampling parallel data. Accordingly, the low-speed data is recovered by means of the existing high-speed SerDes interface, the chip design risk and cost are lowered, and the development cycle is shortened.

Description

[0001] The invention relates to the field of communication technology, in particular to a method and system for recovering low-speed data through a high-speed SerDes interface. Background technique [0002] With the rapid development of ASIC design and IC manufacturing process, the serializer / deserializer (SerDes) interface rate for high-speed data transmission in the chip of communication equipment is rapidly increasing. The SerDes interface rate is generally between 1Gbps and 28Gbps, which can meet the requirements from 1G Ethernet (IEEE802.3z / ab) to 100G Ethernet (IEEE802.3ba / bj). Due to historical reasons, there are still a large number of interfaces with a rate lower than 1 Gbps in the current Ethernet network, and the rate of a typical low-speed Ethernet interface is 100 Mbps (IEEE802.3u) or 10 Mbps. Since the existing high-speed SerDes interface IP increases the central frequency of the phase-locked loop to support higher-rate signals, the existing high-speed SerDes int...

AI Technical Summary

Problems solved by technology

Since the existing high-speed SerDes interface IP increases the central frequency of the phase-locked loop to support higher-rate signals, the existing high-speed SerDes interface IP can no longer support the recovery of 100M data directly through its clock data recovery unit (Clock Data Recovery CDR)

[0003] In order to support the low-speed SerDes interface IP in the Ethernet network, continuing to use the past low-speed process and low-speed SerDes interface IP design chip will lead to the defects of low speed and high power consumption of the entire chip

Re-research and development of low-speed SerDes interface IP under the existing manufacturing process, or transplant the old low-speed SerDes interface IP to the new deep submicron process, the cost of research and development is very high, and there is a risk of adapting to new technologies, and The demand for the old SerDes interface IP is not large, resulting in high cost and poor economic benefits

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