High speed sampler

Abstract

The invention provides a high speed sampler. Signal data are accessed by a signal input module, the accessed signal data are separately transmitted to n delay matrix modules by n channels, each delay matrix module delays the signal data and obtains a plurality of delay data, a synchronization module connected to each delay matrix module performs high-speed synchronous sampling on the plurality of delay data, synchronous sampling is performed a plurality of delayed data just by using a single system clock to obtain a plurality of sampling data, the obtained plurality of sampling data can be equivalent to the sampling data sizes obtained by performing sampling by using a plurality of clocks on different phases at the same time, and thus the problem that the multi-clock phase sampling method is limited by chip process, phase-locked loop precision, output clock channel number, wiring resources and other factors, the sampling rate is difficult to break 4GSa / s in related art is solved.

Description

technical field [0001] The invention relates to the field of high-speed sampling, and more specifically relates to a high-speed sampler. Background technique [0002] The sampling rate is one of the important indicators for judging the performance of the logic analyzer. It directly reflects the ability of the logic analyzer to capture signals. The higher the sampling rate, the higher the timing analysis resolution. [0003] At present, the high-speed sampling of domestic logic analyzers mainly adopts the multi-clock phase sampling method, which requires multiple clocks with different phases to achieve high-speed sampling, but due to factors such as chip technology, phase-locked loop accuracy, output clock channel number, and wiring resources , making it difficult for the sampling frequency to break through 4GSa / s. Contents of the invention [0004] In view of this, the present invention provides a high-speed sampler to increase the sampling frequency, thereby making up fo...

AI Technical Summary

Problems solved by technology

[0003] At present, the high-speed sampling of domestic logic analyzers mainly adopts the multi-clock phase sampling method, which requires multiple clocks with different phases to achieve high-speed sampling, but due to factors such as chip technology, phase-locked loop accuracy, output clock channel number, and wiring resources , making it difficult for the sampling frequency to break through 4GSa / s

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