Design method used for solving VLSI (Very Large Scale Integration) Non-secondary-division layout planning

Abstract

The invention relates to a design method used for solving VLSI (Very Large Scale Integration) Non-secondary-division layout planning. The method comprises the following steps that: (1) in a global search stage, adopting a genetic operator operation to carry out global search, wherein the operator can effectively increase the type of solutions and a possibility for searching an optimal solution; (2) in a local search stage, circularly calling a hybrid simulated annealing algorithm, wherein the algorithm can effectively search the local optimal solution; and (3) in a balance global and local search stage, adopting a mortality probability strategy, wherein the mortality probability strategy reduces the size of a solution space so as to enable the global search and the local search to achieve certain balance. In the strategy, according to a natural rule, each individual in a population can not exist all the time or can not immediately die, on the basis of the rule, and each individual in the population is endowed with a practical age and a dynamic existence age. By use of the method provided by the invention, an efficient and practical layout planning result can be provided, and in addition, a planning result can meet existing VLSI layout planning design requirements.

Description

technical field [0001] The invention relates to a method for solving VLSI indivisible layout planning and design, Background technique [0002] In recent years, with the rapid development of integrated circuit manufacturing technology, the integrated circuit industry has entered the era of nanotechnology, the integration of chips has been further improved, and more and more circuit components can be integrated on a chip. The VLSI design method has been proposed higher requirement. Layout planning is a very important link in the VLSI physical design process, which has a significant impact on the performance indicators of integrated circuits, such as routability, delay characteristics, power consumption, and circuit reliability. With the increasing constraints of the floorplanning problem and the rapid growth of the number of cells on the chip, the algorithm design of the VLSI floorplanning problem poses a huge challenge. Therefore, it is of great significance to seek a more...

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Problems solved by technology

[0005] In addition, the existing layout methods based on analysis methods have the following problems: the analysis-based layout methods mainly use classical optimization algorithms such as linear programming methods to deal with layout problems, and the running time of linear programming methods is variable and equal The exponential times of the number of formulas, which leads to the linear programming method can only deal with small-scale layout planning and design problems

[0006] In addition, with the improvement of science and technology, and the large-scale reduction of the size of the chip, the concentration of electricity on the chip increases, which leads to an increase in heat dissipation and eventually leads to an increase in the temperature of the chip.

However, when the chip temperature exceeds the temperature it can withstand, the chip will fail

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