A Multi-chip Synchronization Architecture Based on Time-to-Digital Converter Circuit

Abstract

The invention discloses a multichip synchronization structure based on a time-digital converter circuit. The multichip synchronization structure comprises N circuit chips provided with built-in time-digital converters and time sequence regulation modules. Each chip contains a synchronization indicating signal receiving end, a synchronization indicating signal output end, one time-digital converter and one time sequence regulation module, wherein the synchronization indicating signal receiving end is used for receiving a synchronization indicating signal input into the chip externally; the synchronization indicating signal output end is used for outputting a synchronization indicating signal subjected to time sequence resampling through a trigger in the chip, wherein the sampling frequency of the trigger is completely aligned with a time sequence of a maximum frequency clock; the time-digital converter is used for quantizing time sequence delays of two input signals into digital values, wherein the input signal IN1 is the synchronization indicating signal input into the chip externally, and the input signal IN2 is the synchronization indicating signal subjected to time sequence resampling through the trigger in the chip; and the time sequence regulation module is used for regulating output delays of the synchronization indicating signals according to the input digital values. By the adoption of a daisy chain structure, the load on a synchronization indicating signal source is relieved.

Description

technical field [0001] The invention relates to a multi-chip synchronization structure based on a time-to-digital converter circuit. It is directly applied to the multi-chip synchronization function realization in high-speed ADC / DAC and high-speed DDS. Background technique [0002] High-speed DDS and DAC chips need to use multiple sets of clock signals with different frequencies, generally the 2 clock signals with the highest frequency N frequency division generated. Such as figure 1 As shown, taking the frequency division by four as an example, when multiple groups of chips are used at the same time, the initial state of the frequency divider inside the chip is different, which will cause the internal clock timing of multiple groups of chips to be different, so that multiple groups of chips cannot work synchronously. [0003] The connection block diagram of the conventional multi-chip synchronization method is as follows: figure 2 shown. Taking the quarter-frequency a...

AI Technical Summary

Problems solved by technology

However, in the case of a huge number of chips and a high operating frequency, the use of this connection method requires a high driving capability of the synchronous indication signal source, and it is difficult to ensure the transmission path of the synchronous indication signal to each chip for PCB board wiring. same length

Therefore, the timing of the synchronization indication signal received by each chip receiving end will have a large deviation, and because the synchronization indication signal source has too much load, the waveform quality of the synchronization indication signal received by each chip receiving end is poor, resulting in conventional multiple Increased probability of errors in chip synchronization methods

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