Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

An Accurate Timing Analysis Method of Block Carry Chain

A technology of timing analysis and carry chain, which is applied in the direction of instrumentation, computing, electrical digital data processing, etc., and can solve the problem of not finding timing analysis, etc.

Active Publication Date: 2020-06-16
CAPITAL MICROELECTRONICS
View PDF8 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] At present, the industry has not found a method for more accurate timing analysis

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • An Accurate Timing Analysis Method of Block Carry Chain
  • An Accurate Timing Analysis Method of Block Carry Chain
  • An Accurate Timing Analysis Method of Block Carry Chain

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments.

[0022] In the embodiment of the present invention, when performing timing analysis, the entire carry chain and jump logic in a PLB are analyzed as a whole, accurate and complete timing information can be obtained, and the correct optimization direction can be pointed out to the timing driver router.

[0023] figure 1 It is a schematic flowchart of an accurate timing analysis method for a block carry chain provided by an embodiment of the present invention. Such as figure 1 As shown, an accurate timing analysis method of a block carry chain include...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to an accurate block carry chain time sequence analysis method, which comprises the following steps that: packaging a carry chain and jump logic in an original level after FPGA (Field Programmable Gate Array) chip distribution is carried out to form a block carry chain; taking the block carry chain as a basic unit to construct a time sequence model, and using the time sequence model to carry out time sequence analysis; and unfolding the block carry chain subjected to the time sequence analysis into the original level, and carrying out wiring on the original level. By use of the method, when the time sequence analysis is carried out, the whole carry chain and jump logic in one PLB (Programmable Logic Block) can be analyzed as a whole, accurate and complete time sequence information can be obtained, and a correct optimization direction is given to a time sequence driven wiring unit.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design in the field of microelectronics, in particular to an accurate timing analysis method of a block carry chain. Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array, FPGA) is a logic device with abundant hardware resources, powerful parallel processing capability and flexible reconfigurable capability. These features make FPGA more and more widely used in data processing, communication, network and many other fields. [0003] The FPGA design process includes: design entry, debugging, functional simulation, synthesis, layout and routing, timing simulation, configuration download and other steps. The layout refers to taking the defined logic and input and output blocks from the map and assigning them to the physical locations inside the FPGA. It is often necessary to choose between the optimal speed and the optimal area. Routing is based on the...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/39G06F30/3312
CPCG06F30/39
Inventor 宋惠远郭敬霞朱延飞李秋艳
Owner CAPITAL MICROELECTRONICS
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com