Wafer testing system and testing method thereof
A test system and test method technology, applied in the direction of single semiconductor device testing, etc., can solve the problems of inability to achieve adaptability and different instructions, and achieve the effects of improving test efficiency, reducing interference, and improving isolation.
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[0037] Wafer test system embodiment:
[0038] refer to figure 1 , figure 1 It is a system block diagram of the test system. There are multiple chips arranged on the wafer, and the multiple chips constitute the chipset 1 to be tested. The test system includes a tester 3, a first relay module 41, a single-chip microcomputer 2, and a second relay module 42 and the third relay module 43, the first relay module 41 is used to connect between the tester 3 and the chipset 1, the tester 3 can perform the first test on the chipset 1, and the first relay module 41 is used to receive The first on-off signal output by the tester 3 then realizes the on-off control of the first relay module 41 by the tester 3 .
[0039] The single-chip microcomputer 2 receives the starting signal of the tester 3, and the single-chip microcomputer 2 stores the key of the program and the chip, which is used to interact with the encrypted data of the corresponding chip. The single-chip microcomputer 2 perfo...
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