Simulation verification system

Abstract

The invention discloses a simulation verification system. The simulation verification system comprises a Verilog verification module, a System Verilog interface module, a System C module and a high-level language module. The Verilog verification module is used for instantiating RTL codes and obtaining first state information and further used for receiving time sequence control information returned by the System Verilog interface module to achieve simulation verification on a chip. The System Verilog interface module is used for processing the first state information to obtain second state information and further used for sending the time sequence control information returned by the System C module. The System C module is used for providing multiple language models and obtaining transaction-level data information and language call instructions according to the second state information and the corresponding language models and further used for generating and sending the time sequence control information according to an algorithm returned by the high-level language model. The high-level language model is used for obtaining and returning corresponding algorithms according to the transaction-level data information and the language call instructions. The application range is wide, and the testing efficiency and the precision of the testing result are improved.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a simulation verification system. Background technique [0002] With the continuous development of the field of process technology, the application of chips is becoming more and more extensive. In the process of chip design, functional verification is a necessary link, and as the complexity of chips continues to increase, the monitoring and control that the verification platform for chip verification needs to support becomes more and more complex. . More importantly, for ultra-large-scale chips, it is not only necessary to evaluate and compare the functions and performance of the chip itself with the reference model, but also to build a complete system with the chip and its external models for simulation verification. [0003] In the prior art, the simulation verification system adopted when the chip is simulated and verified is a pure Verilog verification platform, and the...

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Problems solved by technology

[0004] However, on the one hand, because the interface provided by the EDA simulation verification tool is suitable for calling C / System C or System Verilog, it cannot call higher-level languages. Therefore, when certain functions of some chips need to call higher-level When the simulation verification is carried out in the language of the prior art, the simulation verification system in the prior art cannot meet the requirements. Therefore, the simulation test system in the prior art has a small application range and low test efficiency.

[0005] On the other hand, since the operation between Verilog and the calling language in the simulation verification system in the prior art has no star distinction, the result of the simulation verification is inaccurate

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