Implementation method for bus arbiter for dynamically allocating bandwidth

Abstract

The invention discloses an implementation method for a bus arbiter for dynamically allocating bandwidth. The method includes the steps that arbitration periods with certain length and weights of all modules on a bus are set, and time slot allocation of all the modules is smoothly set in each arbitration period; a register is defined for each module, and the registers are used for storing the number of corresponding time slots missed by the corresponding modules; if all the modules generate data transmission requests, arbitration is executed according to the setting of the time slot allocation; if a certain module does not generate the data transmission request, the following modules sequentially is brought forward by one time slot, and the values of the registers are updated; if the module with high priority generates the data transmission request, a response to the request of the module is made in a priority mode, the current module and the following modules are sequentially delayed by one time slot, and the values of the registers are updated; when the values of the registers reach a threshold value, the registers are reset when the corresponding arbitration periods are completed. According to the technical scheme, the processing logic is simple, the speed of digital logic processing is increased, and the method is suitable for high-speed data processing scenes.

Description

technical field [0001] The invention relates to the field of design methods of arbitrators in integrated circuit design, in particular to a method for realizing a bus arbiter for dynamically allocating bandwidth. Background technique [0002] In integrated circuit design, the data bus mostly adopts a shared or centralized design. Multiple data processing modules (or devices, hereinafter collectively referred to as modules) are connected to the same shared data bus, and obtain bus control rights in time-sharing to complete their own data processing. Transport needs. Therefore, the overall bandwidth of the shared bus must be allocated among these modules accordingly, so as to ensure that each module can obtain sufficient bus usage rights and successfully complete corresponding data transmission operations. The task of allocating bus bandwidth is completed by the bus arbiter. Whether it can provide precise control to match the bandwidth requirements of each module is a main pe...

AI Technical Summary

Problems solved by technology

It is not suitable for some scenarios with strict bandwidth requirements, because the above delay is likely to cause data interruption

[0011] 2. If the data flow of some modules is mostly in burst transmission, this module will occupy a large amount of the bus during the burst transmission process, resulting in insufficient bandwidth occupation of other modules, resulting in a large delay in the data transmission of these modules

[0012] 3. This method will dynamically adjust the module bandwidth according to the actual needs. Therefore, when there are multiple modules connected to the bus, the data flow of other modules may be temporarily interrupted because a module occupies the bus for a long time.

This brief interruption of data flow may cause errors to occur

Especially for modules with the lowest bandwidth requirements, if there is no data stream transmission within the longest tolerance time of the module, it will cause an underflow error in the output of the module

For example, for the Ethernet interface module that transmits the message, this kind of underflow will lead to the occurrence of message transmission error

Images