Test method for semiconductor array device

Abstract

The invention relates to a test method for a semiconductor array device. The test method comprises: a to-be-tested semiconductor array device is processed and a tungsten plug layer is exposed; etching is carried out above a gate conducting layer of the to-be-tested semiconductor array device at a preset interval until the gate conducting layer is exposed; the etched parts are filled with conducting media to form attached contact points; and nano probes that should be in contact with gate contact points are in contact with the attached contact points and electrical characteristic testing of a semiconductor unit within a preset attached contact range is carried out. The method has the following beneficial effects: for semiconductor units, corresponding to drain contact points and source contact points that are not arranged at a testing machine bench with gate contact points simultaneously, attached contact points in conduction with gates are added near the semiconductor units, so that the attached contact points, the drain contact points and the source contact points corresponding to the semiconductor units can be arranged at the testing machine bench simultaneously, so that the electrical characteristic of the semiconductor unit can be tested by using the nano probe testing instrument.

Description

technical field [0001] The invention relates to the technical field of semiconductor testing, in particular to a semiconductor array device testing method. Background technique [0002] In the failure analysis of semiconductor devices, a nanoprobe tester is usually used to test the electrical characteristics of the semiconductor device on the tungsten plug layer of the semiconductor device, and analyze the failure cause of the semiconductor device according to the electrical characteristics. The specific operation is to connect a nanoprobe to the tungsten plug corresponding to the drain, source and gate of the semiconductor device, apply different voltages on the drain, source and gate through the nanoprobe, and obtain the corresponding electrical properties. However, the characteristics of semiconductor array devices (such as memory chips) are: in the tungsten plug layer, each row of semiconductor units shares a gate contact, and the drain contact and source contact are di...

AI Technical Summary

Problems solved by technology

However, the characteristics of semiconductor array devices (such as memory chips) are: in the tungsten plug layer, each row of semiconductor units shares a gate contact, and the drain contact and source contact are different with the position of the semiconductor unit. ;Therefore, limited by the area of ​​the testing machine, the nanoprobe instrument can only test the electrical characteristics of the semiconductor unit within a certain range close to the gate contact; for the semiconductor unit beyond this range, because its drain contact and source The pole contact and the gate contact cannot be placed on the testing machine at the same time, so its electrical characteristics cannot be tested by the nano probe instrument

Images