A multi-objective noc test planning optimization method

Abstract

The invention discloses a multi-target NoC testing planning optimization method, and the method carries out the testing of an IP kernel in an NoC through employing parallel testing method reusing the NoC as a testing access mechanism, saves the testing resources and improving the testing efficiency. On the basis of a quantum multi-target evolution algorithm, the method employs multi-system probability angle coding to replace binary system probability amplitude coding, and is more adaptive to an NoC testing planning problem. The method employs harmonic distance to replace congestion distance, and can balance the congestion degree in a better way. The method employs a chaotic strategy to dynamically update a rotating angle, and gives good consideration to the exploration and mining capability of the algorithm.

Description

technical field [0001] The invention relates to the technical field of Network-on-Chip (NoC), in particular to a multi-objective NoC test planning optimization method. Background technique [0002] The rapid development of integrated circuit manufacturing technology has led to the integration of more and more IP (Intellectual Property) IP cores on a single chip. The traditional bus-based SoC (System-on-Chip) faces low communication bandwidth, difficult clock synchronization, and poor scalability. and other bottlenecks that are difficult to break through. Therefore, some researchers adopt communication-centric design instead of computing-centric design, transplant the idea of ​​computer network into chip design, propose a new NoC (Network-on-Chip) integrated circuit architecture, use grouping and routing The exchange communication technology replaces the traditional bus communication technology, and completely solves the obstacles of the traditional bus SoC communication fro...

AI Technical Summary

Problems solved by technology

However, since the large thermal effect of the chip during the test will destroy the reliability of the chip, it is not only the test time, but also the optimization of the test power consumption is particularly important.

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