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LDPC (low density parity check) decoding optimization method based on flash programming interference error perception

A programming interference and optimization method technology, applied in the direction of response to error generation, encoding, encoding components, etc., can solve the problems of information transmission that does not make full use of flash error mode characteristics, large decoding delay overhead, and does not consider numerical correlation characteristics, etc.

Active Publication Date: 2017-02-01
HUAZHONG UNIV OF SCI & TECH
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Problems solved by technology

[0005] The existing LDPC decoding algorithm has the following obvious deficiencies: 1. The existing LDPC decoding algorithm only considers the internal information transmission and does not make full use of the error mode characteristics of the flash itself, which has high decoding complexity and larger decoding delay overhead; 2. The existing LDPC decoding algorithm does not consider the influence of the numerical correlation feature of the program disturbance error, and does not incorporate this favorable feature into the LDPC decoding information update process; 3. The existing The LDPC decoding algorithm does not provide additional decision information, and simply relies on the characteristics of the decoding mechanism itself to update information

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  • LDPC (low density parity check) decoding optimization method based on flash programming interference error perception
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  • LDPC (low density parity check) decoding optimization method based on flash programming interference error perception

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[0046] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0047] The structural design diagram of the present invention is as follows Figure 4 As shown, when the decoder receives an LDPC codeword, each bit node V j The initial reliability information P of i ,I k Can be obtained, based on the obtained initial reliability information of the bit node, the check node C connected to the bit node i (Look figure 1 and figure 2 ) reliability information ca...

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Abstract

The invention discloses an LDPC (low density parity check) decoding optimization method based on flash programming interference error perception. Along with the increase of NAND flash-memory storage density, more bit information is stored in each unit; the coupling interference along the units is high; the serious programming interference errors are caused, so that the traditional BCH code cannot ensure the data reliability; the LDPC code has error-correcting performance superior to that of the BCH code, and is applied to an NAND flash-memory storage system. The used optimized LDPC decoding algorithm has important significance. Through observation, the programming interference errors have value correlative characters; when the LDPC decoding is performed, the value correlative characters of the programming interference errors can be blended into the LDPC decoding process; the additional information is provided for bit judgment, so that the bit judgment precision is improved; the decoding convergence speed is accelerated; the LDPC decoding delay is reduced.

Description

technical field [0001] The invention belongs to the technical field of solid-state disk storage, and more specifically relates to an LDPC decoding optimization method based on flash programming interference error perception. Background technique [0002] Solid State Disk (SSD for short) based on NAND flash memory has the advantages of high performance, large capacity, anti-vibration, low power consumption and non-volatility, and is widely used in computer storage systems. Solid state disk SSD uses NAND flash memory (NAND flash) as the storage medium. With the improvement of NAND flash manufacturing process, each unit stores more bit information. For example, each unit of MLC NAND flash memory stores two bits of information, and the unit stores less information. The charge and the distance between the cells are relatively close, and the coupling interference between the cells is relatively strong. When a programming operation is performed on a certain page in the NAND flash m...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10H03M13/11
CPCG06F11/1068H03M13/1111
Inventor 吴非谢长生张猛马瑞祥
Owner HUAZHONG UNIV OF SCI & TECH
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