Generation method of optimal net list for functional simulation of large-capacity FPGA (Field Programmable Gate Array) circuit

Abstract

The invention provides a generation method of an optimal net list for functional simulation of a large-capacity FPGA (Field Programmable Gate Array) circuit. The optimal net list can be dynamically generated according to resources utilized by the FPGA circuit. According to the method provided by the invention, all unit names and instantiation unit names of top-layer units in a full-chip net list need to be acquired and configuration files of the full-chip net list are obtained; then a corresponding full-chip net list is generated by matched FPGA software according to placement and routing resource distribution of the FPGA circuit, and module resources, routing resources and configuration resources of a used FPGA can be accurately positioned; finally, the configuration files of the needed resources are added into the full-chip net list and the optimal net list of all the resources used by the FPGA circuit is generated through script processing. According to the requirements of cases for validation, certain functions are pre-configured by utilizing the FPGA and the optimal net list is obtained by adopting the different configuration files. The generation method has a function of flexibly and dynamically configuring the net list and can save simulation resources; the operation speed and the validation efficiency of a simulator are improved and the coverage rate of a validation circuit is improved to the greatest extent.

Description

technical field [0001] The invention relates to a method for verifying full-chip netlist interception, in particular to a method for generating an optimal netlist for function simulation of a large-capacity FPGA circuit, and belongs to the technical field of programmable logic devices. Background technique [0002] With the continuous and rapid development of semiconductor manufacturing technology, the integration of chips is getting higher and higher, and the functions are becoming more and more powerful, and the complexity of chip verification is also increasing. The number of test cases for a system chip is sufficient. Surprisingly, the importance of verification work in the entire chip development process is also increasing. The FPGA chip includes digital circuits and analog circuits, including custom-designed circuits and semi-custom-designed circuits, and contains a large number of programmable resources. In order to verify the correctness of the logic function of the...

AI Technical Summary

Problems solved by technology

In order to verify the correctness of the logic function of the entire FPGA chip, a lot of verification work must be done, but the larger the circuit size, the netlist file can reach 700MB, and the simulation tools based on Candence's ncverilog and Synosys' vcs are used to run large-capacity The functional simulation of the circuit may take up to a week for a verification, and it takes the same time to re-verify after an error is found.

At the same time, it takes up a lot of server resources

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