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A circuit structure and operation method for realizing chained list pipeline operation

A circuit structure and linked list technology, applied in the direction of memory address/allocation/relocation, etc., to achieve the effect of improving processing bandwidth

Active Publication Date: 2019-07-23
众邦同力(武汉)技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is to provide a circuit structure for realizing the pipeline operation of the linked list, solve the problem that the software and the general linked list circuit cannot handle the incoming and outgoing chains at the same time in each clock cycle, and improve the processing bandwidth

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  • A circuit structure and operation method for realizing chained list pipeline operation
  • A circuit structure and operation method for realizing chained list pipeline operation
  • A circuit structure and operation method for realizing chained list pipeline operation

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Embodiment Construction

[0041] The present invention will be further described below in conjunction with specific examples and accompanying drawings.

[0042] The present invention provides a circuit structure for realizing the pipeline operation of the linked list, such as Figure 4 As shown, it includes a linked list storage area and a linked list queue, the linked list storage area includes a next hop pointer and a valid indication of the next hop pointer, and the linked list queue includes a chain head, a chain tail, and a non-null indication of the chain head; the next hop pointer The valid indication is represented by 2 bits, denoted as status0[1:0], its 2 bits are respectively represented as status0[0] and status0[1], and status0[0] is defined to be readable and writable on the inbound side and outbound side can only be read, status0[1] is readable and writable on the outbound side, and can only be read on the inbound side; The status is represented by 2 bits, denoted as status1[1:0], its 2 b...

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Abstract

The invention provides a circuit structure for achieving chain table pipeline operation. The circuit structure comprises a chain table storage area and a chain table queue. The chain table storage area comprises a next-hop pointer and next-hop pointer effective indication. The chain table queue comprises a chain head, a chain tail and non-idle indication of the chain head. The circuit structure is characterized in that the next-hop pointer effective indication status 0[1:0] is expressed by 2 bits, and the 2 bits of the indication are expressed as status 0[0] and status 0[1] respectively; the chain table queue further comprises a reboot chain head and an indication state of the reboot chain head, and the indication state status 1[1:0] of the reboot chain head is expressed by 2 bits; the chain tail contains status 0[0]information corresponding to the chain table storage area. The problem that software and universal hardware chain tables can not process chain inlet and chain outlet at the same time for each clock cycle is solved; processing bandwidth is increased.

Description

technical field [0001] The invention relates to the field of linked list operations, in particular to a circuit structure and an operating method for realizing the linked list pipeline operation. Background technique [0002] The method of operating linked lists based on software is very mature, and the built-in data types of languages ​​such as Lisp and Scheme include the access and operation of linked lists. Currently, the on-chip cache RAM used in chip technology is the most flexible real dual-port RAM, which has two independent readable and writable operation ports, and the pipeline operation circuit structure is as follows: figure 1 As shown, the pipeline operation waveform is as follows figure 2 shown. Since the first entry into the chain needs to update the chain head and the non-empty indication of the linked list while updating the tail of the chain, the effective indication of the storage area of ​​the linked list needs to be updated when entering the chain, and...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/02
CPCG06F12/02
Inventor 姚树建许进
Owner 众邦同力(武汉)技术有限公司
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