Array substrate, manufacturing method thereof and display panel

Abstract

The invention relates to an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a substrate body, test lines formed on the substrate body, an electrostatic shielding graph formed above the test lines and an insulating layer formed between the electrostatic shielding graph and the test lines. The electrostatic shielding graph includes a main body portion and an electrostatic leading portion. The electrostatic leading portion is connected with the main body portion, extends to a pressing connection area and is suitable for pressing connection on a driving circuit on the array substrate. In the array substrate, due to the fact that the electrostatic shielding graph including the electrostatic leading portion is arranged above the test lines, when anti-static testing is conducted on the array substrate, the main body portion gives priority to absorb electrostatic charges, the electrostatic charges are led to the driving circuit press-connected onto the array substrate through the electrostatic leading portion, the amount of the electrostatic charges entering the array substrate through the fracture surface positions of the test lines can be decreased, poor electrostatic discharge can be avoided, the probability of internal circuit damage and abnormal display can be reduced.

Description

technical field [0001] The present invention relates to the field of display technology, and in particular, to an array substrate, a manufacturing method thereof, and a display panel. Background technique [0002] After the array process is completed, it is necessary to use testing equipment to test to confirm the yield rate of the array process and the incidence of various defects. The specific testing process is as follows: using the probes of the testing equipment to contact the array substrate, and loading test signals on the test lines on the array substrate to realize the test. Among them, the test line is specially designed for testing, and is generally designed in the process design stage. In the subsequent process after the test is completed, part of the test lines outside the cutting line will be cut off through the cutting process, and only part of the test lines within the cutting line will be retained, such as figure 1 Array substrates formed by dicing shown i...

AI Technical Summary

Problems solved by technology

Since the section of the test line formed after cutting is exposed, the insulation cannot be completely sealed, so during the antistatic test, the electrostatic charge will enter the panel from the section of the test line and discharge in the internal circuit of the panel, resulting in electrostatic discharge ( Electro-Static discharge, referred to as ESD) is bad, destroying the internal circuit, resulting in abnormal display

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