Network transmission real-time audio-video error correction method and system based on FPGA

Abstract

The invention discloses a network transmission real-time audio-video error correction method and a network transmission real-time audio-video error correction system based on an FPGA, and relates to the field of digital video broadcasting technologies. The technical points of the method provided by the invention comprise analyzing data packets remotely transmitted via a network, processing the data packets matched with a local IP address and a local port number, and judging a check FEC packet and a data RTP packet and respectively storing into the internal RAM and external SDRAM of the FPGA. The check FEC packet is used for recovering the related data RTP packet, the recovered data RTP packet is written back into the SDRAM, a control module reads the complete data packet in the SDRAM for outputting, and thus the loss packet recovery of network remote transmission is achieved.

Description

technical field [0001] The invention relates to the technical field of digital video broadcasting, in particular to an error correction and recovery technology for remote transmission of audio and video. Background technique [0002] SMPTE: Society of Motion Picture and Television Engineers; [0003] FEC: forward error correction; [0004] FIFO: first in first out memory; [0005] RTP: Real-time Transport Protocol; [0006] IP: A protocol for interconnecting networks. [0007] Packet loss occurs in the long-distance data transmission of the digital video broadcasting network, especially when the transmission distance is long and the network environment is poor. This will seriously affect the reception of video broadcasting, causing freezes and mosaics in the received TV programs, and even more serious packet loss will make the receiving end unable to work normally. It is necessary to carry out error control transmission on the data stream of digital video broadcasting, ...

AI Technical Summary

Problems solved by technology

[0010] Solution 1 is easy to implement and does not occupy external storage resources. However, the internal RAM resources of the FPGA are limited. Due to the limitation of cached data packets, this solution cannot solve the problem of data packet jitter, and the error correction capability is also weak.

[0011] Solution 2 can solve the shortcomings of solution 1, but it is not very economical to use 2 pieces of SDRAM

[0012] Solution 3 can recover low-speed data streams, but cannot handle high-speed data streams, especially for networks with high packet loss rates.

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