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Method and apparatus for optimizing integrated circuit noise performance

An integrated circuit and noise technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of many long wirings, inability to insert short wirings into long wirings, etc., to achieve the effect of optimizing noise performance

Active Publication Date: 2019-05-07
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, in a target area, the number of routes to be processed may be close to the number of channels in the area, or the number of long routes to be routed is large, making it impossible to insert short routes or blank channels between long routes

Method used

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  • Method and apparatus for optimizing integrated circuit noise performance
  • Method and apparatus for optimizing integrated circuit noise performance
  • Method and apparatus for optimizing integrated circuit noise performance

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Embodiment Construction

[0018] Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0019] figure 1 A block diagram of an exemplary computer system / server 12 suitable for use in implementing embodiments of the invention is shown. figure 1 The computer system / server 12 shown is only an example and should not impose any limitation on the functions and scope of use of the embodiments of the present invention.

[0020] Such as figure 1 As shown, computer system / server 12 takes the form of a general purpose computing devic...

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Abstract

The present invention discloses methods and apparatus for optimizing the noise performance of integrated circuits. The method is used to arrange the target wiring in the target area, and the method includes: for each wiring in the target wiring, obtaining its signal transition interval for every other wiring in the target wiring, wherein one wiring is for another wiring The signal transition interval is the time interval between the signal transition of the one wiring and the signal transition on the other wiring; the corresponding time impact factor is calculated according to the signal transition interval, wherein the The time influence factor is a decreasing function of the signal transition interval; and the target wiring is arranged in the target area according to the time influence factor. By adopting the technical solutions according to the embodiments of the present invention, the coupling noise between wirings can be reduced.

Description

technical field [0001] The present invention relates to the art of integrated circuit design, and more particularly, to methods and apparatus for optimizing the noise performance of integrated circuits. Background technique [0002] The development of integrated circuit manufacturing technology makes the chip density higher and higher. Coupling noise between wires is also becoming more and more prominent. Coupling noise can cause coupling deltadelay in the wiring, which will destroy the signal timing. Therefore, it is necessary to strictly control the wiring during IC design. [0003] Those skilled in the art can understand that when the area in the integrated circuit is divided into a small enough area, all wirings in the area are parallel to each other. In the following description, it is assumed that all routings are parallel to each other, ie only adjustments are made to routings in a small enough area. Those skilled in the art can easily extend the method according ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCG06F30/394G06F30/398G06F2119/10
Inventor 汤晓峰浦索明于渤李侠
Owner INT BUSINESS MASCH CORP
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