High-speed low-power-consumption dynamic comparator

Abstract

The invention discloses a high-speed low-power-consumption dynamic comparator, comprising a pre-amplification circuit and a regeneration latch circuit; the pre-amplification circuit comprises a clock output end, a first differential signal input end, a second differential signal input end, an output node FN and an output node FP; the pre-amplification circuit is connected with a direct current power, the output node FN synthesizes the output voltage VDD of the direct current power and a first differential input signal to output the first differential input signal, and the output node FP synthesizes the output voltage VDD of the direct current power and a second differential input signal to output the second differential input signal; the regeneration latch circuit is connected with the output node FN and the output node FP of the pre-amplification circuit, and can be used for latching the first differential input signal and the second differential input signal and outputting a first output signal and a second output signal. The dynamic comparator provided by the invention can quickly achieve low power consumption dynamic latching function under the high speed application.

Description

technical field [0001] The invention relates to the technical field of analog integrated circuits, in particular to a dynamic comparator with high speed and low power consumption. Background technique [0002] Comparator (Comparator) is an important component module of many integrated circuits (IC), such as analog-to-digital converter (ADC), transconductance amplifier (OTA), voltage reference source (VR) and clock data recovery circuit (CDR), through detection The differential input voltage produces a corresponding output that displays input voltage information with a larger magnitude. In modern communication systems, with the ever-increasing demand for lighter weight and smaller size in portable devices, comparators need to achieve high-speed operation with low power consumption and low cost. However, with the reduction of advanced CMOS process size (to 40nm and 28nm, even smaller), the power supply voltage of the core circuit is also reduced, but the threshold voltage of ...

AI Technical Summary

Problems solved by technology

However, the input stage of this structure still requires a high common-mode voltage, which can cause trouble at low supply voltages; in addition, a pair of differential clock signals is required in the dual-tailed dynamic comparator, which brings additional area and Power Consumption and Possible Timing Issues

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