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Statistical timing analysis method used for post-silicon adjustable register circuits

A timing analysis, register technology, applied in instrumentation, computing, electrical digital data processing, etc.

Inactive Publication Date: 2016-06-15
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The difficulty of this problem is that the number of cycles in a cyclic graph is exponentially related to the number of edges

Method used

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  • Statistical timing analysis method used for post-silicon adjustable register circuits
  • Statistical timing analysis method used for post-silicon adjustable register circuits
  • Statistical timing analysis method used for post-silicon adjustable register circuits

Examples

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Embodiment 1

[0097] Embodiment 1 is used to illustrate the main steps of the method of the present invention.

[0098] The present invention is used for the statistical timing analysis method of the post-band silicon adjustable register circuit. The implementation steps are as follows: figure 1 shown.

[0099] image 3 (a) is an example of a sequential circuit with logic path delays. image 3 (b) is its corresponding timing constraint. image 3 Each vertex in (b) represents image 3 A register in (a). image 3 Each logical path in (a) corresponds to image 3 (b) Two timing constraint edges. E.g, image 3 (a) from FF 1 to FF 2 The logical path delay for is 3. from FF 1 to FF 2 The maximum and minimum delays are both 3. So, image 3 In (b), two corresponding timing constraint edges should be added. Edge (1, 2) corresponds to the setup time constraint as:

[0100] t i -t j ≤T-3.

[0101] Edge (1, 2) corresponds to the hold time constraint as:

[0102] t i -t j ≤3.

[0...

Embodiment 2

[0122] Example 2 is used to show that the statistical timing analysis method proposed by the present invention can significantly reduce the program running time while obtaining comparable accuracy to the existing method.

[0123] In this embodiment, the settings similar to those in [17] are adopted. The results obtained by the Monte Carlo method with 10,000 sampling points are used as the comparison standard for judging the accuracy. The test circuit is from ISCAS89, and the basic unit gates in the test circuit are mapped to the SMIC 65nm unit library. In this embodiment, each register has a post-silicon adjustable register, and the adjustment range of each register is set to 0.3 times the longest path delay of the circuit. In the Monte Carlo method and the method of the present invention, 6 random variables (transistor length, transistor width, threshold voltage of NMOSFET and PMOSFET) are used to model process fluctuations. The standard deviation of these independent rando...

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Abstract

The invention belongs to the technical field of integrated circuits, and in particular relates to a statistical timing analysis method for a post-band silicon adjustable register circuit. The method includes: compressing the pivot to obtain N independent random variables; generating sparse grid configuration points; calculating the minimum clock period of each configuration point; calculating the minimum clock period generalized polynomial chaos expansion coefficient; calculating the post-silicon adjustable register circuit yield rate. The method has high feasibility, can significantly reduce the program running time while obtaining the accuracy comparable to the existing method, and can be used to solve the statistical timing analysis problem of large-scale post-band silicon adjustable register circuits.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and relates to a statistical timing analysis method for a post-band silicon adjustable register circuit. technical background [0002] As IC feature sizes shrink below 100nm, process variation has become one of the major challenges to circuit timing performance. Post-silicon tunable clock tree is a powerful technique to fix timing violations caused by process variation [1,2]. In post-silicon tunable clock trees, post-silicon tunable registers are inserted into the clock tree during the design phase. The delay of the post silicon adjustable register can be adjusted by changing the control signal. A typical post-silicon tunable register structure such as figure 2 Shown in [1]. After the chip is produced, the time margin of the register state can be balanced by changing the delay of the post-silicon tunable register. This process is called post-silicon tuning. During post-silicon tu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 曾璇杨帆朱恒亮周海杨运峰周星宝
Owner FUDAN UNIV
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