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FPGA method achieving computation speedup and PCIESSD storage simultaneously

An algorithm and accelerator technology, applied in the field of FPGA, can solve the problems of increasing enterprise cost, increasing power consumption, occupying multiple server slots, etc., to achieve the effect of reducing overall power consumption, reducing cost, and reducing layout difficulty

Inactive Publication Date: 2016-06-15
FASII INFORMATION TECH SHANGHAI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although enterprise-level GPU accelerator cards have strong computing power, they are expensive and consume high power consumption, which increases the cost of enterprises
Compared with GPU accelerator cards, FPGA accelerator cards are cheaper and have lower power consumption. However, using PCIe SSD and FPGA accelerator cards at the same time not only occupies multiple server slots, but also increases power consumption, which increases the cost of the enterprise.

Method used

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  • FPGA method achieving computation speedup and PCIESSD storage simultaneously
  • FPGA method achieving computation speedup and PCIESSD storage simultaneously

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Embodiment Construction

[0011] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0012] see figure 1 , in the embodiment of the present invention, a kind of FPGA method that simultaneously realizes computing acceleration and PCIESSD storage uses a piece of FPGA, integrates SSD controller and algorithm accelerator in FPGA, also includes SSD controller in FPGA, and described SSD controller It is realized by the logic in FPGA, manages and controls the flash memory array of SSD, and the SSD controller communicates with the server node through ...

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Abstract

The invention discloses an FPGA method achieving computation speedup and PCIE SSD storage simultaneously. An FPGA is used, an SSD controller and an algorithm accelerator are integrated in the FPGA, the FPGA is further internally provided with a DDR controller and a direct memory read module DMA, and the direct memory read module DMA is connected with the SSD controller, the DDR controller and the algorithm accelerator respectively. According to the FPGA method achieving computation speedup and PCIE SSD storage simultaneously, the two functions of computation speedup and SSD storage are achieved on PCIE equipment, the layout difficult is reduced, overall power consumption of server nodes is reduced, and the cost of an enterprise is reduced.

Description

technical field [0001] The invention relates to an FPGA method, in particular to an FPGA method for simultaneously realizing calculation acceleration and PCIESSD storage. Background technique [0002] With the rapid development of informatization, the demand for high-density computing is increasing, and the computing power and storage IO (input / output) capabilities of a single server node are required to be higher and higher. At present, the enterprise market widely adopts PCI ESSD to improve the IO capability of storage; and for computing power, GPU (Graphics Processing Unit) accelerator card or FPGA accelerator card is generally used. Although enterprise-level GPU accelerator cards have strong computing capabilities, they are expensive and consume high power consumption, which increases the cost of enterprises. Compared with GPU accelerator cards, FPGA accelerator cards are cheaper and consume less power. However, using both PCI ESSD and FPGA accelerator cards will not on...

Claims

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Application Information

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IPC IPC(8): G06F13/16G06F13/28G06F15/78
CPCG06F13/1668G06F13/282G06F15/78Y02D10/00
Inventor 肖飞
Owner FASII INFORMATION TECH SHANGHAI
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