Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Functional verification method and platform for ddr3 SDRAM controller

A function verification and controller technology, applied in instruments, static memory, etc., can solve problems such as limiting DDR3 SDRAM read and write performance, achieve the effect of convenient maintenance and upgrade, convenient maintenance and upgrade, and reduce the chance of omissions and errors

Active Publication Date: 2018-11-06
SHENZHEN PANGO MICROSYST CO LTD
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These delay requirements objectively limit the read and write performance of DDR3 SDRAM

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Functional verification method and platform for ddr3 SDRAM controller
  • Functional verification method and platform for ddr3 SDRAM controller
  • Functional verification method and platform for ddr3 SDRAM controller

Examples

Experimental program
Comparison scheme
Effect test

test Embodiment 11

[0033] Test case 11, used to detect the correctness of user read and write operations, specific user interface timing or signals;

[0034] The port monitoring module 12 designed with hierarchical and object-oriented technology is used to detect the correctness of the DDR3 SDRAM port signal.

[0035] In some embodiments, the port monitoring module 12 in the above-mentioned embodiments is used to encapsulate the signal of the DDR3 SDRAM port into a command service in units of commands, monitor and analyze the command service according to the state table, and determine the DDR3 SDRAM port signal according to the analysis result correctness.

[0036] In some embodiments, the port monitoring module 12 in the above embodiments is also used to set the main content, logical structure, member variables and member methods of the command service.

[0037] In some embodiments, the logic structure in the above embodiments is a tree logic structure including commands, non-MRS commands, arr...

no. 2 example

[0041] figure 2 The flow chart of the function verification method provided by the second embodiment of the present invention is composed of figure 2 It can be seen that, in the present embodiment, the function verification method for the DDR3 SDRAM controller provided by the present invention comprises the following steps:

[0042] S201: The test case detects the correctness of user read and write operations, specific user interface timing or signals;

[0043] S202: A port monitoring module designed with layered and object-oriented technology is used to detect the correctness of the DDR3 SDRAM port signal.

[0044]In some embodiments, the port monitoring module in the foregoing embodiments detects the correctness of the DDR3 SDRAM port sequence: the signal of the DDR3 SDRAM port is encapsulated as a command service in units of commands, and the command service is monitored and analyzed according to the state table, according to The analysis result confirms the correctness...

no. 3 example

[0050] The present invention will be further explained in combination with specific application scenarios.

[0051] The agreement stipulates many timing constraints of DDR3 SDRAM in operation. These timings are complex and easy to omit during verification. Therefore, how to effectively find an architecture that can effectively organize these constraints in time and space is an important issue. question. The role of the verification platform in chip verification determines that the code of the verification platform should be easy to maintain and robust; in addition, considering the future development of the DDR series, it also needs to have good adaptability to facilitate future possible new additions. Function, only need to add and modify a small amount of code to upgrade the verification platform.

[0052] Based on the above-mentioned technical status, this embodiment provides a test platform using System Verilog language programming. The overall structure of the test platfo...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a function verification method and platform for a DDR3 SDRAM (double data rate 3 synchronous dynamic random access memory) controller. The function verification method comprises steps as follows: adopting a test case to detect correctness of user read-write operation, specific user interface timing sequences or signals; adopting a port monitoring module designed with layering and object oriented technologies to detect correctness of DDR3 SDRAM port signals. According to the invention, the design of the port monitoring module adopts layering and object oriented design methods, so that various timing sequence constraints at a DDR3 SDRAM port are effectively organized in the aspects of time and space, the probability of omission is low, and maintenance and upgrading are facilitated.

Description

technical field [0001] The invention relates to the verification field of DDR3 SDRAM controllers, in particular to a function verification method and platform for DDR3 SDRAM controllers. Background technique [0002] DDR3 SDRAM is the third generation of high-performance DDR SDRAM (double data rate synchronous dynamic random access memory, double data rate synchronous dynamic random access memory) proposed to adapt to the development of computer technology. Compared with the previous generation of DDR2 SDRAM, The advantages of its greater data rate, greater data capacity and lower power supply voltage make it more suitable for the requirements of the new generation of storage technology. In addition, DDR3 SDRAM also adopts new technologies such as ODT (on-line debugging technique, online debugging technology) to further ensure the signal integrity of data during high-speed transmission. [0003] The DDR3 SDRAM protocol stipulates that the data transmission is completed by i...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/56
CPCG11C29/56
Inventor 蒋德
Owner SHENZHEN PANGO MICROSYST CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com