Single-event-resistant reinforced clock and data recovery circuit

Abstract

The invention discloses a single-event-resistant reinforced clock and data recovery circuit, which comprises a sampling apparatus, a phase discriminator, a digital filter, a logic judgment circuit, an encoder, a majority decision device, a phase interpolator and a multiphase clock generation circuit. The circuit adopts the logic judgment circuit, transfer of a phase discrimination error of the phase discriminator and a filtering error of the filter, which are caused by a single event effect, into subsequent encoder circuits can be effectively restrained under the condition that the clock and data recovery circuit is locked, so that the correctness of the signal transferred to the encoder is guaranteed; a coding error caused by the single event effect is restrained through a redundant structure of the encoder, so that accidental adjustment of the locked clock and data recovery circuit is effectively avoided, the influence of the single event effect on the phase lock state is greatly reduced, and the reliability of the circuit is improved.

Description

technical field [0001] The invention relates to a clock and data recovery circuit, in particular to a single-event-resistant clock and data recovery circuit realized by a digital algorithm and a redundant structure, belonging to the field of high-speed radiation-resistant circuit design. Background technique [0002] Clock and data recovery circuits are the key blocks to realize high-speed serial communication. It recovers the clock signal from the serial data, finds the best sampling point of the data through the adjustment of the circuit, recovers the data through the retiming of the data, eliminates the jitter introduced in the data transmission process, and its performance has a great impact on the entire high-speed serial The line transmission system has a crucial influence. The clock and data recovery circuit is an indispensable key circuit in the high-speed serial data communication system, and it is also the main bottleneck for the system to increase to a higher rat...

AI Technical Summary

Problems solved by technology

In integrated circuit structures, these excess carriers can deposit charge in unexpected places, causing transients in the circuit's node voltages and in the current flow through the device

The existing clock and data recovery circuit structure does not have an anti-single event effect structure. When the phase is locked, the circuit node voltage transient of different units or the current transient across the device may be caused by the single event effect, which may cause the circuit Various errors occur, which make the phase-locked clock and data recovery circuit make wrong adjustments, resulting in phase lock-out, which in turn leads to data sampling errors, and finally increases the bit error rate of data transmission and reduces the operating efficiency of the entire system. reliability

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