Method of operating simulator compensating for delay and device for perofmring the same

Abstract

A simulator includes a memory for storing a first netlist, a timing library, and a standard parasitic exchange format (SPEF) file; and a processor configured to compensate for delay to synchronize digital and analog signals. The processor includes a delay calculator module for generating one of a rising time and a falling time and a standard delay format (SDF) file using the first netlist, the timing library, and the SPEF file; an SDF file converter module for adjusting an interconnect delay description included in the SDF file to compensate for delay using the one of the rising time and the falling time; and a digital simulator module for generating an event using a first driving cell according to a compensated interconnect delay description.

Description

[0001] Priority is claimed on Korean Patent Application No. 10-2014-0142459 filed with the Korean Intellectual Property Office on October 21, 2014, the entire contents of which are hereby incorporated by reference. technical field [0002] Embodiments of the inventive concept relate to a method of operating a simulator, and more particularly, to a method of operating a simulator and a simulation device for performing the method, wherein the simulator is capable of including a The interconnect delay description in the (SDF) file compensates for the synchronization of the digital signal with the analog signal. Background technique [0003] Electronic Design Automation (EDA) is a technology for designing and producing electronic devices ranging from printed circuit boards (PCBs) to embedded circuits. Mixed-signal simulation tools for EDA are commonly used to verify semiconductor designs such as semiconductor memory or system-on-chip (SoC). [0004] Mixed-signal simulators may ...

AI Technical Summary

Problems solved by technology

However, D / A signal conversion or A / D signal conversion can cause timing errors when the digital and analog domains are connected to each other

Such timing errors can degrade the accuracy of digital or analog modeling

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