Eight-bit serial-parallel conversion driving chip suitable for heavy-current control driving

Abstract

The invention discloses an eight-bit serial-parallel conversion driving chip suitable for heavy-current control driving. The chip comprises a low-voltage voltage-stabilizing unit, a detection processing unit, a communication unit and a driving unit, wherein the low-voltage voltage-stabilizing unit is connected with an additionally arranged power source; the detection processing unit monitors a load state output by the chip in real time; the communication unit comprises one eight-bit shift register and one eight-bit data latch register for receiving external serial input data signals, realizing an eight-bit serial-parallel conversion function and sending parallel output signal data to the driving unit for driving a load; and the driving unit receives the signal data of the communication unit and drives the load based thereon. The chip provided by the invention has a load open-circuit and short-circuit detection function and a short-circuit protection function and guarantees communication stability; and the problem of difficulty in driving a load needing to be driven by heavy currents due to low output power of a conventional serial-parallel conversion chip is solved, the chip cost is greatly decreased, and the chip has a great significance on product development and batch production.

Description

technical field [0001] The invention belongs to the field of chip control, in particular to an 8-bit serial-to-parallel conversion drive chip suitable for large current control drive. Background technique [0002] 74HC595 is a CMOS device with a silicon structure, compatible with low-voltage TTL circuits, and complies with the JEDEC NO.7A standard. [0003] 74HC595 has 8-bit shift register and a memory, three-state output function. The shift register and memory have independent clocks. [0004] Data is input into the shift register on the rising edge of SH_cp (shift register clock input), and is input into the storage register on the rising edge of ST_cp (memory clock input). If the two clocks are tied together, the shift register will always be one pulse ahead of the storage register. [0005] The shift register has a serial shift input (Ds), and a serial output (Q7'), and an asynchronous low-level reset, and the storage register has a parallel 8-bit bus output with thre...

AI Technical Summary

Problems solved by technology

[0012] Using ULN2803 to connect 74HC595 serial-to-parallel conversion chip and high-current drive control equipment solves the problem of insufficient output capacity of 74HC595, but also increases the manufacturing cost

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