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Digital self-calibration circuit and method of successive approximation analog-to-digital converter

An analog-to-digital converter and successive approximation technology, applied in the direction of analog/digital conversion calibration/testing, can solve the problems of increasing design area, reducing design performance, etc., and achieve the effect of reducing delay

Active Publication Date: 2018-10-26
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Claims
  • Application Information

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Problems solved by technology

Traditional solutions such as increasing the capacitor area will seriously increase the design area or reduce the design performance

Method used

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  • Digital self-calibration circuit and method of successive approximation analog-to-digital converter
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  • Digital self-calibration circuit and method of successive approximation analog-to-digital converter

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Embodiment Construction

[0049] 为了便于理解,现以一个具体的逐次逼近型模数转换器为例说明本发明实施例的数字自校准电路,具体的逐次逼近型模数转换器如 figure 1 所示;逐次逼近模数转换器包括第一电容阵列101、第二电容阵列102、校准电容阵列105、比较器(COMP)103、控制逻辑电路(SAR&CAL Logic)104和存储器(CAL Memory)106。由第一电容阵列101和第二电容阵列102组成权重电容阵列。

[0050] 所述第一电容阵列101的输出端PX连接到所述比较器103的第一输入端且通过一切换开关SP连接到共模电平VCM,所述第二电容阵列102的输出端NX连接到所述比较器103的第二输入端且通过一切换开关SN连接到共模电平VCM,由所述第一电容阵列101和所述第二电容阵列102组成伪差分电容阵列。

[0051] 所述第一电容阵列101包括第一段子电容阵列和一个以上的低位段子电容阵列,所述第一段子电容阵列为位数比各所述低位段子电容阵列都高。

[0052] 所述第一段子电容阵列包括多位电容,各所述低位段子电容阵列包括多位电容,所述第二电容阵列102的电容位数比所述第一段子电容阵列的电容位数多一个,所述第二电容阵列102的最高位电容到次低位电容依次和相同位的所述第一段子电容阵列的电容大小相等并组成差分权重位电容;所述第二电容阵列102的最低位电容和次低位电容大小相等。

[0053] 模数转换过程中,首先从所述第一段子电容阵列的最高位到最低位进行逐位的差分权重位的模数转换,所述第一段子电容阵列的最低位差分权重位转换完成后,将所述最低位差分权重位码值转换成过渡码值;当所述最低位差分权重位码值为1时,所述过渡码值使所述第二电容阵列102的次低位电容和最低位电容都接地;当所述最低位差分权重位码值为0时,所述过渡码值使所述第二电容阵列102的次低位电容和最低位电容都接参考电压VREF。

[0054] 所述过渡码值转换完成后,由所述第一段子电容阵列的最低位电容和所述低位段子电容阵列的电容组成单端权重位模式电容阵列并进行单端权重位的转换。

[0055] 所述校准电容阵列105包括多位电容,所述校准电容阵列105的输出端和所述第二电容阵列102的输出端通过耦合电容CNS连接,所述校准电容阵列105用于对所述伪差分电容阵列的电容的失配...

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Abstract

The invention discloses a digital self-calibration circuit of a successive approximation analog-to-digital converter. During analog-to-digital conversion, when carrying out kth bit analog-to-digital conversion, one control code is selected from two selectable control codes according to former bit data at first, and the selected control code is used for controlling a calibration capacitor array and calculating the kth bit data; and before outputting the kth bit data, when carrying out the kth bit analog-to-digital conversion, a logic circuit is controlled to calculate the two selectable control codes corresponding to the (k-1) th bit. The invention further discloses a digital self-calibration method of a successive approximation analog-to-digital converter. The digital self-calibration circuit and method disclosed by the invention can be used for improving the conversion efficiency and the conversion precision, reducing the number of adders and saving the circuit area.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a digital self-calibration circuit of a successive approximation analog-to-digital converter (Successive Approximation Register ADC, SAR ADC). The invention also relates to a digital self-calibration method of the successive approximation analog-to-digital converter. Background technique [0002] Successive approximation analog-to-digital converters are widely used in various fields. In the design of the successive approximation analog-to-digital converter, the main errors come from the mismatch of the capacitance and the offset of the comparator. Among them, the capacitance mismatch error introduced during manufacturing has the greatest impact on the performance of the ADC. Traditional solutions such as increasing the capacitor area will seriously increase the design area or reduce the design performance. Therefore, we choose to use on the basis of segment cap...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/10
Inventor 尹涛张斌
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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