Capacitor switching and averaging method for improving linearity of successive approximation analog-digital converter

Abstract

The invention discloses a capacitor switching and averaging method for improving the linearity of a successive approximation analog-digital converter, and relates to the field of microelectronics and solid state electronics, and in particular to successive approximation analog-digital converters. No correction algorithm needs to be introduced, the capacitance does not need to be split, high capacitance DAC and low capacitance DAC only need to be exchanged between two transformations, bit circulation is carried out on remaining bits for twice, and two transformation results are averaged to obtain a final output codeword. The capacitor switching and averaging method provided by the invention can be used for avoiding accumulating errors of capacitor mismatch at the same codeword, therefore, compared with a traditional correction method of improving the linearity by a correction algorithm, the capacitor switching and averaging method has the advantages that the structure is simpler, a smaller chip area is occupied and on-chip implementation is easier.

Description

technical field [0001] The invention relates to the field of microelectronics and solid state electronics, in particular to a successive approximation analog-to-digital converter. Background technique [0002] ADCs convert real-world analog signals into digital signals, and the performance of the ADC has a huge impact on the stability, reliability, and durability of the device. In recent years, the rapid development of digital signal processing technology has led to an increasing demand for high-speed, high-precision, low-power analog-to-digital converters (ADCs). ADCs are generally divided into fully parallel analog-to-digital converters (FlashADC), pipeline analog-to-digital converters (PipelineADC), oversampling analog-to-digital converters (ΣΔADC), and successive approximation analog-to-digital converters (SARADC). The figure of merit (FOM) represents the energy required for each conversion step of the ADC, and is an important indicator to measure the design level of th...

AI Technical Summary

Problems solved by technology

The binary capacitive successive approximation analog-to-digital converter is based on the "trial and error method". Its biggest advantage is that each capacitor is connected to a fixed level, so the linearity is good. The disadvantage is that the number of required unit capacitors increases exponentially with the accuracy. , and it is difficult to match the minimum capacitance to the maximum capacitance, generally used in analog-to-digital converters with an accuracy less than 10 bits

[0008] Generally speaking, due to the limitation of the current process conditions, the capacitor can only meet the matching accuracy of 10 bits, and it is not easy to achieve high precision. Therefore, the high-precision successive approximation analog-to-digital converter mainly relies on the LMS algorithm to correct the mismatch of the capacitor, while the traditional The calibration scheme based on the LMS algorithm has high precision and good calibration effect under the condition of given error modeling, but if the initial value is not selected properly, it will increase the complexity of the algorithm, and even lead to problems such as non-convergence of the algorithm, which is not easy to implement on-chip

Images