Device and method used for SDH (Synchronous Digital Hierarchy) clock jitter test

Abstract

The invention discloses a device and a method for an SDH (Synchronous Digital Hierarchy) clock jitter test. The device comprises a power module, a signal input module, a photovoltaic conversion module, a differential amplification module, a clock recovery module, a tracking clock recovery module, a jitter recovery module, a signal conditioning module, an A / D (Analog / Digital) conversion module, a FPGA (Field Programmable Gate Array) jitter test module, a PXI (PCI extensions for Instrumentation) bus control module and an upper computer module. Firstly, the device adopts the FPGA jitter test module to omit expensive test instruments and save the cost of the SDH clock jitter test. Secondly, the device adopts an integrated clock recovery chip ADN2812, a differential amplifier ADL5566, an interface chip PCI9054 and the like, so that the area and the complexity of a test circuit are reduced, and the use of a PLL (Phase Locked Loop) circuit is reduce. Finally, the device adopts a way that the upper computer module controls and tests the FPGA jitter test module to reduce the use of an analog circuit and cause a SDH clock jitter test result to be more reliable.

Description

technical field [0001] The invention relates to the field of SDH clock jitter, in particular to a device and method for testing SDH clock jitter. Background technique [0002] Jitter test is one of the core contents of digital clock signal integrity test in SDH (Synchronous Digital Hierarchy), and it is one of the most important measurement parameters of SDH signal quality test; in digital synchronous communication network, the jitter of transmission clock affects the system Synchronization, excessive jitter may also directly lead to bit errors, or reduce the signal-to-noise ratio of the signal, so it is very important to test the jitter of the clock of the SDH signal. However, when traditionally measuring the jitter of the SDH clock, it is often necessary Expensive instruments are used to generate data streams with jitter components, which greatly increases the cost of SDH clock jitter measurement; on the other hand, in order to load jitter, many new circuits are added, whi...

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Problems solved by technology

[0002] Jitter test is one of the core contents of digital clock signal integrity test in SDH (Synchronous Digital Hierarchy), and it is one of the most important measurement parameters of SDH signal quality test; in digital synchronous communication network, the jitter of transmission clock affects the system Synchronization, excessive jitter may also directly lead to bit errors, or reduce the signal-to-noise ratio of the signal, so it is very important to test the jitter of the clock of the SDH signal. However, when traditionally measuring the jitter of the SDH clock, it is often necessary Expensive instruments are used to generate data streams with jitter components, which greatly increases the cost of SDH clock jitter measurement; on the other hand, in order to load jitter, many new circuits are added, which increases a lot of extra area; at the same time, Most circuits loaded with jitter are implemented by analog circuits. However, analog circuits often change with changes in voltage, temperature and process, and cannot accurately measure the amplitude and frequency of clock jitter signals.

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