Shifting register and driving method thereof as well as gate drive circuit and display device
A technology for shift registers and gates, which is applied in the field of gate drive circuits, display devices, and shift registers, and can solve problems that affect the stable output of shift registers, large noises in scanning signals, and unstable gate potentials, etc.
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example 1
[0126] by Figure 2a The structure of the shift register shown is taken as an example to describe its working process, in which Figure 2aIn the shift register shown, all switching transistors are N-type switching transistors, each N-type switching transistor is turned on under the action of a high potential, and turned off under the action of a low potential; the potential of the first DC signal vn1 is a high potential, The potential of the second DC signal vn2 is a low potential; the potential of the first reference signal cn1 is a high potential, and the potential of the second reference signal cn2 is a low potential; the corresponding input and output timing diagram is as follows Figure 4a shown. Specifically, choose Figure 4a The input-output timing diagram shown has four stages: the input stage S1, the output stage S2, the reset stage S3 and the reset hold stage S4.
[0127] In the input stage S1, ck1=0, ck3=0, input=1, reset=0.
[0128] Since reset=0, the third sw...
example 2
[0138] by Figure 3a The structure of the shift register shown is taken as an example to describe its working process, in which Figure 3a In the shift register shown, all switching transistors are N-type switching transistors, each N-type switching transistor is turned on under the action of a high potential, and turned off under the action of a low potential; the potential of the first DC signal vn1 is a high potential, The potential of the second DC signal vn2 is a low potential; the potential of the first reference signal cn1 is a high potential, and the potential of the second reference signal cn2 is a high potential; the corresponding input and output timing diagram is as follows Figure 4b shown. Specifically, choose Figure 4b The input-output timing diagram shown has four stages: the input stage S1, the output stage S2, the reset stage S3 and the reset hold stage S4.
[0139] In the four stages of the input stage S1, the output stage S2, the reset stage S3 and the ...
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