System for dynamically detecting state of railway retarder based on FPGA
A dynamic detection and deceleration technology, applied in general control systems, control/regulation systems, and program control in sequence/logic controllers, etc., can solve problems such as misjudgment of deceleration quality and lack of deceleration data analysis, etc. To achieve the effect of improving detection efficiency
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[0019] Below in conjunction with accompanying drawing, preferred implementation of the present invention is described in further detail:
[0020] see figure 1 , the FPGA-based railway deceleration top state dynamic detection system of the present invention includes a central processing unit module 1, an AD acquisition module 2, a USB storage module 3, a PWM differential output module 4, a photoelectric encoding pulse counting module 5, and an RS232 Serial port output display module 6 and a power supply module 7, AD acquisition module 2, USB storage module 3, PWM differential output module 4, photoelectric code pulse counting module 5, RS232 serial port output display module 6, and power supply module 7 are all connected with the central processing unit module 1 connection.
[0021]The CPU module is composed of FPGA control chip, clock circuit, reset circuit, SDRAM memory chip, EPCS memory chip, AS interface circuit and JTAG interface circuit. The control driver drives the se...
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