Method for verifying large-scale interconnection chips based on BFM

Abstract

The invention discloses a method for verifying large-scale interconnection chips based on a BFM, and belongs to the field of chip design. The method comprises the steps that operation of sending a bus protocol command is achieved through utilizing routers and physical layer accesses of the chips between BFM simulation nodes; the BFM is connected with the chips of the same node through pli interfaces, the BFM simulates socket models between the nodes, and BFM logic verification environment is established; a system C simulates a CPU to send a drive signal to the logic verification environment at the BFM end, the socket models send verification data to chips through the pli interfaces, after the chips respond, chip feedback data are recorded, and error detection records are achieved through the system C. By means of the method for verifying the large-scale interconnection chips based on the BFM, the complexity degree of verification is reduced, the comprehensive validation is guaranteed, the universality of verification drive is improved, and by means of the advantage of taking the system C as a software language, the operation and the data monitoring with higher abstraction degree are achieved.

Description

technical field [0001] The invention discloses a method for verifying large-scale interconnected chips based on BFM, which belongs to the field of chip design. Background technique [0002] The long-distance between chips is applied through interconnection. With the continuous improvement of high-speed and high-density interconnection requirements, the scale of large-scale interconnection chip CC is getting larger and larger. The transmission characteristics of large-scale interconnection chips and chip configuration, etc. Factors affect the function of the chip after interconnection. Among them, the correlation between functional modules is relatively large, there are many connection signals, and the circuit is complicated. It is necessary to perform functional verification on the chip after interconnection to ensure that the chip after large interconnection reaches the level of the chip. Configuration requirements to be able to complete functional tasks. However, with the...

AI Technical Summary

Problems solved by technology

[0005] The present invention aims at the problem that the traditional verification environment of large-scale interconnection chips will greatly increase the workload and complexity of integrated circuit verification, and cannot meet the existing verification requirements of interconnection chips, and provides a method for verifying large-scale interconnection chips based on BFM The method is suitable for any type of design, especially in the design of a relatively large test space or a large number of interactive scenarios. Using BFM is to encapsulate the bus function in a model, which can be called by calling the task , simulate the bus timing, realize various bus functions

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