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Superscale pipeline reservation station processing instruction method and device

A technology for processing instructions and reserved stations, applied to machine execution devices, concurrent instruction execution, etc., can solve problems such as increasing the complexity of memory access operations and execution segment control, and reducing the performance of microprocessor execution segments

Inactive Publication Date: 2015-06-17
SHENZHEN STATE MICROELECTRONICS CO LTD
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  • Claims
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AI Technical Summary

Problems solved by technology

[0014] The purpose of the embodiments of the present invention is to provide a method for processing instructions at a reservation station of a superscalar pipeline. Memory operation and execution segment control complexity, and reduce the problem of microprocessor execution segment performance

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  • Superscale pipeline reservation station processing instruction method and device
  • Superscale pipeline reservation station processing instruction method and device
  • Superscale pipeline reservation station processing instruction method and device

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Embodiment Construction

[0034] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0035] refer to Figure 4 , Figure 4 It is an implementation flowchart of a method for processing instructions in a superscalar pipeline reservation station provided by an embodiment of the present invention, and is described in detail as follows:

[0036] In step S401, determine the judgment rules of the relevant instruction and the non-relevant instruction;

[0037] In the embodiment of the present invention, the judging rules for determining the relevant instructions and the non-relevant instructions can be set by the user or set by the system.

[0038] Wherein, the judging rule includes at ...

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Abstract

The invention is suitable for the technical field of micro-processors and provides a superscale pipeline reservation station processing instruction method and device. The superscale pipeline reservation station processing instruction method comprises the steps of determining a judgment rule of a correlation instruction and a non-correlation instruction; obtaining each instruction written in an operation queue in multiple pipelines; judging the correlation among the instructions according to the judgment rule, and recognizing the instructions to be the correlation instructions or the non-correlation instructions; caching the correlation instructions into a first type reservation station according to the instruction written-in sequence in the operation queen, and caching the non-correlation instructions into a second reservation station, wherein the correlation instructions refers to the instructions that a calling sequence exists in calculation results or operation parameters in the operation queue, the non-correlation instructions are the instructions except for the correlation instructions in the operation queue, and the first reservation station and the second reservation station are different reservation stations. The superscale pipeline reservation station processing instruction method and device improve the performance of pipeline performing section parallelism processing.

Description

technical field [0001] The invention belongs to the technical field of microprocessors, and in particular relates to a method and a device for processing instructions at a reservation station of a superscalar pipeline. Background technique [0002] Through pipeline technology, the microprocessor executes different instructions in parallel at each stage to improve the performance of the processor. Pipeline technology divides the process of instruction execution into several stages, and implements parallel processing of instructions by executing different instructions in different stages. [0003] refer to figure 1 , figure 1 It is an implementation flowchart that divides instruction execution into instruction fetching, decoding, dispatching, launching, and executing stages. [0004] Instructions must be dispatched in the pipeline before execution can begin. [0005] There are two types of pipelines, one is scalar pipeline and the other is superscalar pipeline. [0006] I...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
Inventor 康海容施懿钱少雄邱均华
Owner SHENZHEN STATE MICROELECTRONICS CO LTD
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