High-speed bridge device for AHB (advanced high-performance bus) accessing on-chip SRAM (static random access memory) and operating method of high-speed bridge device

Abstract

The invention discloses a high-speed bridge device for an AHB (advanced high-performance bus) accessing an on-chip SRAM (static random access memory), which comprises a register and a plus one counter; during write operation, an SRAM address, i.e. an AHB address of the previous clock cycle, which is obtained after an AHB address is stored by the register for a beat is accessed; during read operation, at the beat of returning read operation data, a predicted address which is obtained after the plus one counter adds one to the AHB address is accessed, and at the beat of incomplete read operation data transmission, the AHB address is the SRAM address, i.e., the current AHB address is accessed. The invention also discloses an operating method of the high-speed bridge device for the AHB accessing the on-chip SRAM. The invention uses the buss bridge with an address prediction mechanism to accelerate the read-write access of the high-capacity SRAM, thus increasing the operating efficiency of the whole system.

Description

technical field [0001] The invention relates to the field of high-speed data processing, in particular to a high-speed bridge device for AHB bus accessing on-chip SRAM and a working method thereof. Background technique [0002] In a system with a high-speed peripheral interface and capable of complex data processing functions, SRAM usually plays the role of data temporary storage. The original intention of using large-capacity SRAM is to improve system efficiency, because in various storage devices, the order of read and write speeds from fast to slow is registers, SRAM, DRAM, FLASH, and traditional hard disks. In the SOC system, the CPU, which is often used in the form of IP, has its own cache to improve efficiency, and there is an interface for operating the cache inside. When other data flow control modules of the system need to cache data, they can choose to mount a large-capacity SRAM on the bus as a cache. The advantage is that it can be used for scheduling by mul...

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The efficiency of the whole system decreases accordingly

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