Off-core cache device

Abstract

An off-core cache device comprises a slave device interface unit, a control unit, a storage unit, a master device unit and a synchronizing unit. The slave device interface unit receives and responds to an access request of a master unit. The control unit processes the request transmitted by the slave device interface unit, according to configuration information of a register, gains access to the storage unit or transmits the request to the master device interface unit, and refills cache lines. The storage unit caches data written by the control unit and mark information thereof. The master device interface unit is used for transmitting an access request to a next-level storage device and acquires cache data required. The synchronizing unit converts the access request transmitted by the master device interface unit, into a signal meeting a clock timing sequence of the next-level storage device. The off-core cache device has the advantages that access relay of a nonvolatile memory is effectively decreased, and memory accessing performance of a processor is improved.

Description

technical field [0001] The invention relates to the field of system chip (SoC) integrated design, in particular to an out-of-core cache device. Background technique [0002] With the continuous improvement of the integrated circuit technology level, the integration scale of the system-on-chip (SoC) is getting larger and larger, and the functions are becoming more and more complex and powerful. In order to meet the diverse application requirements, non-volatile memory, such as EEPROM, FLASH, etc., are integrated into the SoC chip, and the capacity is getting larger and larger. [0003] On-chip non-volatile memory usually stores programs and important data, which has an important impact on system startup and execution. Especially for NorFlash, the processor can directly read the stored instruction data and execute the program. However, since the reading speed of NorFlash is much lower than the clock frequency of the processor, this execution method will cause a performance b...

AI Technical Summary

Problems solved by technology

However, the cache integrated in the processor core is tightly coupled with the processor, which is often not flexible enough. It is not designed for the access characteristics of NorFlash or other non-volatile memories, and it is difficult to modify it. The integration is difficult.

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