Instruction scheduling method and device

Abstract

An instruction scheduling method and device for scheduling instructions, relating to the field of communications, that enable a processor or an assembly line to function normally and enhance the accuracy of scheduling. The method comprises: establishing a data dependency graph; extracting from the data dependency graph k instructions to conduct scheduling to obtain m very long instruction words (VLIW) for each cycle such that the VLIW in a same cycle can be executed parallelly and that for any two adjacent cycles, there is no dependency between the instruction at the t-th instruction slot of any VLIW in the latter cycle and the instruction at the (t+1)-th instruction slot of any VLIW in the former cycle, where 0≤k≤m*n, n is the number of instruction slots in a VLIW, n is an integer greater than or equal to 1, m is the number of VLIW in each cycle, m is an integer greater than or equal to 1, and t is an integer greater than or equal to 1 and smaller than or equal to n-1.

Description

technical field [0001] The present invention relates to the communication field, in particular to an instruction scheduling method and device. Background technique [0002] In the prior art, each functional unit in a CPU (Central Processing Unit, central processing unit) is usually independent and parallel, so the compiler uses an instruction scheduling method based on the CPU structure to improve instruction-level parallelism. Among them, instruction scheduling is a technology for executing instructions in parallel. The compiler or machine hardware adjusts the order of instructions to increase the number of instructions executed by the machine in each shot. The shot is the machine execution simulated by the compiler when compiling the source program. clock cycle of the instruction. In the existing compilation technology, a table scheduling algorithm is usually used to implement instruction scheduling, and a candidate instruction queue is usually used. Specifically, when s...

AI Technical Summary

Problems solved by technology

If the instruction scheduling method of table scheduling in the prior art is used to complete the instruction scheduling on the multi-core processor, when the instructions are executed, instructions with dependencies may be executed at the same beat or the next instruction that depends on this instruction precedes this instruction Execution occurs, these situations may cause the processor to run incorrectly or the pipeline to stall, and the scheduling accuracy is low

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