A Pipeline Commitment Method for Store Instructions in a Superscalar Microprocessor

Abstract

The invention relates to a method for realizing streamline retiring of a store instruction in a superscalar microprocessor. The method is characterized in that the automatic sequencing function of buffer of three types is utilized, the interface protocol of the buffer of the three types is improved, the executing conditions of the store instruction are weakened, and therefore, the retiring of the store instruction is sped up. According to the method, the quantity of instructions retired in each clock period and the quantity of the store instruction of writing first-stage data cache in each clock cycle are properly allocated, thus the store instruction streamline retiring function can be realized under the condition that the store address hits the first-stage data cache and the writing is authorized when executing the continuous store instruction sequence, and as a result, the performance of the microprocessor can be obviously improved.

Description

technical field [0001] The invention relates to the completion and submission logic of memory access instructions of a superscalar microprocessor, in particular to a pipeline submission method for realizing storage instructions in a superscalar microprocessor. Background technique [0002] Current superscalar microprocessors support out-of-order issue, out-of-order execution, speculative execution, and in-order commit, such as figure 1 As shown, the instruction pipeline usually includes several basic pipeline platforms such as Fetch, Decode, Register Rename (Map), Issue, Execute, and Retire. It is a basic design requirement to submit instructions in program order after execution is completed. Therefore, current superscalar microprocessors are equipped with a full instruction reordering buffer (ROB). This buffer is a circular queue with head and tail pointers. All instructions entering the pipeline The instructions are registered to the tail of the ROB in program order. Aft...

AI Technical Summary

Problems solved by technology

It can be seen that the write DCache operation of the Store instruction depends on the submission time of the previous instruction. Even if it hits the first-level data cache and has writable permission, the Store instruction cannot be submitted together with the older instruction, so Submitting Store instructions is very slow

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