A method for optimizing a field-programmable gate array chip layout

Abstract

The invention relates to a method for optimizing a field-programmable gate array chip layout, the method comprising: initiating a temperature value T; selecting a basic unit, creating a first cost function in accordance with a length of an interconnection line between the basic unit and other basic units, and the time delay of the interconnection line; generating in random a second coordinate value of the basic unit, creating a second cost function in accordance with a length of an interconnection line between the basic unit represented by the second coordinate value and other basic units and the time delay of the interconnection line; determining whether the generated second coordinate value is accepted as a new solution according to a difference value of the second cost function from the first cost function and a current temperature value; based on the new solution of each basic unit in said each LE, updating a preset hierarchical net list; reducing the temperature value until the temperature value is less than a designated threshold value or the generated second coordinate value is continuously not received. When processing a layout circuit in a large scale, the method of optimizing a chip layout of the invention can speed up the running speed of the algorithm, and reduce the running time of a program.

Description

technical field [0001] The invention relates to a layout algorithm, in particular to a layout optimization method of a field programmable logic gate array chip. Background technique [0002] Currently, in Field Programmable Gate Array (Field Programmable Gate Array, FPGA) applications, integrated circuits are required to have a programmable or configurable interconnection network, and logic gates are connected to each other through the configurable interconnection network. FPGAs, functioning as stand-alone chips or as a core part of a system, have been widely used in a large number of microelectronic devices. The definition of FPGA logic gates in a broad sense not only refers to simple NAND gates, but also refers to logic units (LE, Logic Element) of combinational logic and sequential logic with configurable functions or logic composed of multiple logic units interconnected Piece. [0003] With the expansion of the scale of FPGA chips, the layout algorithm is becoming more...

AI Technical Summary

Problems solved by technology

Therefore, when the simulated annealing layout algorithm deals with large-scale layout circuits, the processing time is too long due to the large size of the layout circuit, which often fails to meet the user's requirements for program running time.

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