Method for manufacturing MOS transistor with cascaded and stacked nanowires

Abstract

A stacked nanowire MOS transistor and a manufacturing method therefor. The stacked nanowire MOS transistor comprises multiple nanowire stacks, multiple gate stacks, multiple source and drain regions, and multiple channel regions. The nanowire stacks extend along a first direction (Y-Y') on a substrate (1). The gate stacks extend along a second direction (X-X') and cross each nanowire stack. The source and drain regions are located on two sides of each gate stack along the second direction (X-X'). The channel regions are formed by the nanowire stacks among the multiple source and drain regions. The multiple nanowire stacks are stacks formed by multiple cascaded nanowires. By performing etch-backs, performing side etching on the channels and performing filling many times, cascaded nanometer stacks with good quality are formed and the effective width of electric conduction channels are fully increased by using low cost, and the total electric conduction area is improved, thereby improving a driving current.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor device, in particular to a novel method for manufacturing a cascaded stacked nanowire MOS transistor. Background technique [0002] In the current sub-20nm technology, the three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances the gate control ability and suppresses leakage and short channel effects. [0003] For example, compared with traditional single-gate bulk Si or SOI MOSFETs, MOSFETs with double-gate SOI structures can suppress short-channel effects (SCE) and drain-induced barrier lowering (DIBL) effects, have lower junction capacitance, and can To achieve light channel doping, the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about 2 times the driving current and reduce the requirements for the effective gate oxide thickness (EOT). Compared with the double-gate device, the gate ...

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Problems solved by technology

This method is severely limited by the quality of the epitaxial thin layer, which greatly increases the process cost

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