Ion implantation method for improving PMOS device performance

Abstract

The invention provides an ion implantation method for improving PMOS device performance. The method comprises steps: at least one first transistor region and at least one second transistor region separated by an isolation area are formed on a silicon substrate, a first gate is formed on the first transistor region, and a second gate is formed on the second transistor region; a silicon nitride layer is deposited on the silicon substrate to enable the silicon nitride layer to fully cover the first transistor region, the second transistor region, the first gate and the second gate; a photoresist is applied to the silicon substrate to enable the photoresist to fully cover the first transistor region, the second transistor region, the first gate and the second gate; photoetching is carried out on the photoresist to remove the photoresist covering the first transistor region and the first gate; ultraviolet light treatment is carried out on the first transistor region; the photoresist in the second transistor region is removed; and dry etching is carried out on the silicon nitride layer so as to form side walls covering two sides of the first gate and side walls covering two sides of the second gate, and side walls at the top part of the gate and the source / drain end are etched and removed.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, more specifically, the invention relates to an ion implantation method for improving the performance of a PMOS device. Background technique [0002] When the device size enters the range of deep submicron trench length, the electric field strength inside the device increases with the decrease of the device size, especially there is a strong electric field near the drain junction, and the carriers obtain higher energy in this strong electric field and become heat carrier. Hot carriers affect device performance in two aspects: 1) cross the Si-SiO2 barrier, inject into the oxide layer, accumulate continuously, change the threshold voltage, and affect device life; 2) interact with the crystal in the depletion region near the drain The lattice collision generates electron-hole pairs. For NMOS tubes, the electrons generated by the collision form an additional leakage current, and the holes a...

AI Technical Summary

Problems solved by technology

But for PMOS, because of the small atomic mass of boron, the diffusion is fast, and the performance of the device is easily affected by the size of the sidewall.

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